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| Boilerpipe Text | 2.5D
Multiple chips arranged in a planar or stacked configuration with an interposer for communication.
2D Materials
3D NAND
Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.
But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.
Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.
In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.
In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.
One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.
The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.
Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.
Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.
Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a âmacaroni channel,â according to Objective Analysis.
Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.
Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.
3D Transistors
Transistors where source and drain are added as fins of the gate.
3D-ICs
2.5D and 3D forms of integration
5G
Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.
6G
A brief history of design
We start with schematics and end with ESL
A brief history of logic simulation
Important events in the history of logic simulation
A brief history of logic synthesis
Early development associated with logic synthesis
Acronyms
Commonly and not-so-commonly used acronyms.
The following is a list of acronyms and what they stand for:
ACK - Acknowledge
ADC - Analog to Digital Converter
AI - Artificial Intelligence
ALD - Atomic Layer Deposition
ALE - Atomic Layer Etch
AMOLED - Active-Matrix OLED
AMP - Asymmetric Multi Processing
AOI - Automated Optical Inspection
AP - Access Point
ASIC - Application Specific Integrated Circuit
ATE - Automatic Test Equipment
BEOL - Back-End-Of-Line
BGA - Ball Grid Array
BSA - Basic Service Area
BTI - Bias-Temperature Instability
CA - Collision Avoidance
CBRAM - Conductive Bridging RAM
CCI - Cache Coherent Interconnect
CD Collision Detection
CF - Contention-Free
CFP - Contention-Free Period
CP - Contention Period
CPU - Central Processing Unit
CRC - Cyclic Redundancy Check
CSMA - Carrier Sense, Multiple Access
CFD - Computational Fluid Dynamic
CMOS - Complementary Metal Oxide Semiconductor
CNN - Convolutional Neural Network
CPP - Contacted Poly Pitch
CSP - Chip Scale Packaging
CTS - Clear To Send
DAC - Digital to Analog Convertor
DARPA - Defense Advanced Research Projects Agency
DCF - Distributed Coordination Function
DDR - Double Data Rate
DFA - Differential Fault Analysis
DFT - Design for Test
DFM - Design for Manufacturing
DIFS - Distributed Inter-frame Space
DPA - Differential Power Analysis
DL - Deep Learning
DRAM - Dynamic Random Access Memory
DRC - Design Rule Checker
DSA - Directed Self Assembly
DSP - Digital Signal Processor
DUT - Design Under Test
DUV - Design Under Verification
DVFS - Dynamic Voltage and Frequency Scaling
ECO - Engineering Change Order
EDA - Electronic Design Automation
EM - Electromagnetic
EM - Electromigration
ESL - Electronic System Level
EUV - Extreme Ultraviolet
FD-SOI - Fully Depleted Silicon on Insulator
FEOL - Front-End-Of-Line
FET - Field Effect Transistor
FIFO - First In First Out
FPGA - Field Programmable Gate Array
GAA - Gate-All-Around
GaAs - Gallium Arsenide
GaN - Gallium Nitride
GPU - Graphics Processing Unit
HBM - High Bandwidth Memory
HBT - Heterojunction Bipolar Transistor
HDL - Hardware Description Language
HMC - Hybrid Memory Cube
IC - Integrated Circuit
IEEE - Institute of Electrical and Electronics Engineers
IIC - Industrial Internet Consortium
IIoT - Industrial Internet of Things
IoT - Internet of Things
IP - Intellectual Property
IR - Infra-red
ISM - Industrial, Scientific, Medical
ISS - Instruction Set Simulator
ILT - Inverse Lithography Technology
JTAG - Joint Test Action Group
LAN - Local Area Network
LCD - Liquid Crystal Display
LTE - Long-Term Evolution
MAC -Media Access Control
MCU - Microcontroller
MEMS - Micro Electrical Mechanical Systems
MES - Manufacturing Execution Systems
ML-Machine Learning
MOL - Middle-Of-Line
MRAM - Magnetic Random Access Memory
NA - Numerical Aperture
NGL - Next-Generation Lithography
NIC - Network Interface Card
NSF - National Science Foundation
NVM - Non-Volatile Memory
OCAP - Out of Control Action Plan
OLED - Organic Light-Emitting Diode
OPC - Optical Proximity Correction
OS - Operating System
OSAT - Outsourced Semiconductor Assembly and Test
OTP - One Time Programmable
PCB - Printed Circuit Board
PCF - Point Coordination Function
PCM - Phase-Change Memory
PDK - Process Design Kit
PDN - Power Delivery Network
PHY - Physical Layer
PI - Power Integrity
PIFS - Point Inter-frame Space
PnR - Place and Route
PoP - Package-on-Package
PPA - Power, Performance, Area
PPAC - Power, Performance, Area, Cost
PRNG - Pure Random Number Generator
PVT - Process, Voltage, Temperature
RAM - Random Access Memory
RC4 - Rivest Cipher 4
RDL - Register Definition Language
RDL - Redistribution Layer
RF - Radio Frequency
ROM - Read Only Memory
RoT - Root Of Trust
RTL - Register Transfer Level
RTOS - Real Time Operating System
RTS - Request To Send
SCM - Storage Class Memory
SerDes - Serializer / Deserializer
SIFS - Short Inter-frame Space
SI - Signal Integrity
SiC - Silicon Carbide
SiGe - Silicon Germanium
SK - Shared Key
SMP - Symmetric Multi Processing
SoC - System on Chip
SOI - Silicon on Insulator
SPA - Simple Power Analysis
SRAF - Sub-Resolution Assist Features
SRAM - Static Random Access Memory
SSD - Solid-state Storage Drives
SSID - Service Set Identifier
STA - Static Timing Analysis
STI - Shallow Trench Isolation
TLM - Transaction Level Model
TSV - Through Silicon Via
UPF - Unified Power Format
USB - Universal Serial Bus
UVM - Universal Verification Methodology
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
VSLI - Very Large Scale Integration
VIP - Verification Intellectual Property
VoWi-Fi - Voice over Wi-Fi
Vt - theshold Voltage
Wan - Wide Area Network
WEP - Wired Equivalency Protocol
Wi-Fi - Wireless High Fidelity
WiGIG - Gigabit Wi-Fi
WLAN - Wireless Local Area Network
WLP - Wafer Level Packaging
WPA - Wi-Fi Protected Access
ADAS: Advanced Driver Assistance Systems
Sensing and processing to make driving safer.
Advanced Packaging
Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.
While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.
These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.
Advanced Packaging Fundamentals eBook (2025-2026)
Agile
An approach to software development focusing on continual delivery and flexibility to changing requirements
Agile Hardware Development
How Agile applies to the development of hardware systems
Air Gap
A way of improving the insulation between various components in a semiconductor by creating empty space.
Amdahlâs Law
The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.
Analog
Semiconductors that measure real-world conditions
Analog circuits
Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.
Analog Design and Verification
The design and verification of analog components.
Application Programming Interface (API)
A software tool used in software programming that abstracts all the programming steps into a user interface for the developer.
Application Specific Integrated Circuit (ASIC)
A custom, purpose-built integrated circuit made for a specific task or product.
Application-Specific Standard Product (ASSP)
An IC created and optimized for a market and sold to multiple companies.
Architectures
Artificial Intelligence (AI)
Using machines to make decisions based upon stored knowledge and sensory input.
Assertion
Code that looks for violations of a property
Atomic Force Microscopy (AFM), Atomic Force Microscope (AFM)
A method of measuring the surface structures down to the angstrom level.
Atomic Layer Deposition (ALD)
A method of depositing materials and films in exact places on a surface.
Atomic Layer Etch (ALE)
ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.
Automatic Test Equipment (ATE)
Automatic Test Pattern Generation (ATPG)
The generation of tests that can be used for functional or manufacturing verification
Automotive
Issues dealing with the development of automotive electronics.
Automotive Ethernet, Time Sensitive Networking (TSN)
Time sensitive networking puts real time into automotive Ethernet.
Automotive Standards
Autonomous Vehicles
Avalanche Noise
Noise in reverse biased junctions
AVM
Verification methodology created by Mentor
Backend-of-the-line (BEOL)
IC manufacturing processes where interconnects are made.
Backside Power Delivery Network (BPDN)
Bandgap, Band Gap
Batteries
Devices that chemically store energy.
Behavioral Synthesis
Transformation of a design described in a high-level of abstraction to RTL
Blech Effect
A reverse force to electromigration.
Bluetooth, Bluetooth Low Energy (BLE)
Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.
Brazil
BSIM
Transistor model
Built-in self-test (BiST)
On-chip logic to test a design.
Bunch of Wires (BoW)
Chiplet interconnect specification.
Bus Functional Model
Interface model between testbench and device under test
C, C++
C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.
Cache Coherent Interconnect for Accelerators (CCIX)
Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.
CD-SEM: Critical-Dimension Scanning Electron Microscope
CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.
CDC design principles
Making CDC interfaces predictable
Cell-Aware Test
Fault model for faults within cells
Cell-Aware Test for FinFET
Cell-aware test methodology for addressing defect mechanisms specific to FinFETs.
Central Processing Unit (CPU)
The CPU is an dedicated integrated circuit or IP core that processes logic and math.
Characterization/Metrology Lab
A lab that wrks with R&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.
Checker
Testbench component that verifies results
Chemical Vapor Deposition (CVD)
A process used to develop thin films and polymer coatings.
China
Chip Design
Design is the process of producing an implementation from a conceptual form
Chip Design and Verification
The design, verification, implementation and test of electronics systems into integrated circuits.
Chip Thermal Interface Protocol
Exchange of thermal design information for 3D ICs
Chiplet Fundamentals For Engineers: 2026 eBook
Chiplets
A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.
There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.
With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.
A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.
Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandouâs chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandouâs interconnect technology.
DARPAâs approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.
The CHIPS program started in 2017. The program has various types of contractors/sub-contractorsâmanufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).
Clock Domain Crossing (CDC)
Asynchronous communications across boundaries
Clock Gating
Dynamic power reduction by gating the clock
Clock Tree Optimization
Design of clock trees for power reduction
CMOS
Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.
CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.
Co-Packaged Optics
Code Coverage
Metrics related to about of code executed in functional verification
Combinatorial Equivalence Checking
Verify functionality between registers remains unchanged after a transformation
Companies & Organizations
Compiled-code Simulation
Faster form for logic simulation
Complementary FET (CFET)
Complementary FET, a new type of vertical transistor.
Compound Semiconductors
Combinations of semiconductor materials.
Compute Express Link (CXL)
Interconnect between CPU and accelerators.
Contact
The structure that connects a transistor with the first layer of copper interconnects.
Convolutional Neural Network (CNN)
A technique for computer vision based on machine learning.
Coverage
Completion metrics for functional verification
Crosstalk
Interference between signals
Crypto processors
Crypto processors are specialized processors that execute cryptographic algorithms within hardware.
Dark Silicon
A method of conserving power in ICs by powering down segments of a chip when they are not in use.
Data Analytics
Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.
Data Analytics & Test
How semiconductors are sorted and tested before and after implementation of the chip in a system.
Data Movement
The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.
Debug
The removal of bugs from a design
Deep Learning (DL)
Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.
Definitions
Dennardâs Law
An observation that as features shrink, so does power consumption.
Deposition
Design for Manufacturing (DFM)
Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.
Design for Test (DFT)
Techniques that reduce the difficulty and cost associated with testing an integrated circuit.
Design Patent
Protection for the ornamental design of an item
Design Rule Checking (DRC)
A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer
Design Rule Pattern Matching
Locating design rules using pattern matching techniques.
Device Noise
Sources of noise in devices
DFT and Clock Gating
Insertion of test logic for clock-gating
Diamond Semiconductors
A wide-bandgap synthetic material.
Digital IP
Categorization of digital IP
Digital Oscilloscope
Allowed an image to be saved digitally
Digital Signal Processor (DSP)
A digital signal processor is a processor optimized to process signals.
Digital Twins
A digital representation of a product or system.
Directed Self-Assembly (DSA)
A complementary lithography technology.
DNA biometrics
DNA analysis is based upon unique DNA sequencing.
Domain/Distributed Architecture
Double Data Rate (DDR)
Double Patterning
A patterning technique using multiple passes of a laser.
Double Patterning Methodologies
Colored and colorless flows for double patterning
DRAM: Dynamic Random Access Memory
Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.
Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.
In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.
DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.
Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.
The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.
Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these
The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.
Dynamic Voltage and Frequency Scaling (DVFS)
Dynamically adjusting voltage and frequency for power reduction
e
Hardware Verification Language
E-beam Inspection
A slower method for finding smaller defects.
E-Beam Lithography
Lithography using a single beam e-beam tool
EBooks by Semiconductor Engineering
EDA & Design
Edge AI
Edge Computing
Edge Placement Error (EPE)
The difference between the intended and the printed features of an IC layout.
Electromigration
Electromigration (EM) due to power densities
Electronic Design Automation (EDA)
Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.
Electronic System Level (ESL)
Levels of abstraction higher than RTL used for design and verification
Electrostatic Discharge (ESD)
Transfer of electrostatic charge.
Embedded FPGA (eFPGA)
An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.
Emulation
Special purpose hardware used for logic verification
Energy Harvesting
Capturing energy from the environment
Engineers: Jobs & Education
Environmental Noise
Noise caused by the environment
Epitaxy
A method for growing or depositing mono crystalline films on a substrate.
eRM
Reuse methodology based on the e language
Error Correction Code (ECC)
(where you are)
Methods for detecting and correcting errors.
Ethernet
Ethernet is a reliable, open standard for connecting devices by wire.
EUV: Extreme Ultraviolet Lithography
EUV lithography is a soft X-ray technology.
Failure Analysis
Finding out what went wrong in semiconductor design and manufacturing.
Fan-Outs
A way of including more features that normally would be on a printed circuit board inside a package.
Fault Simulation
Evaluation of a design under the presence of manufacturing defects
Ferroelectric FETs (FeFET)
Ferroelectric FET is a new type of memory.
Field Programmable Gate Array (FPGA)
Reprogrammable logic device
FinFET
A three-dimensional transistor.
Flash Memory
Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.
The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.
Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.
With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.
Flexible Hybrid Electronics (FHE)
Integrated circuits on a flexible substrate
FlexRay ISO 17458
An automotive communications protocol
Flicker Noise
Noise related to resistance fluctuation
Flip-Chip
A type of interconnect using solder balls or microbumps.
Forksheet FET
A transistor type with integrated nFET and pFET.
Formal Verification
Formal verification involves a mathematical proof to show that a design adheres to a property
Foundry, pure-play foundry
A company that specializes in manufacturing semiconductor devices.
Functional Coverage
Coverage metric used to indicate progress in verifying functionality
Functional Design and Verification
Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.
Functional Verification
Functional verification is used to determine if a design, or unit of a design, conforms to its specification.
Gage R&R, Gage Repeatability And Reproducibility
A statistical method for determining if a test system is production ready by measuring variation during test for repeatability and reproducibility.
Gallium Nitride (GaN)
GaN is a III-V material with a wide bandgap.
Gate-All-Around FET (GAA FET)
A transistor design with a gate is placed on all four sides of the channel.
Gate-Level Power Optimizations
Power reduction techniques available at the gate level.
Generation-Recombination Noise
noise related to generation-recombination
Generative Adversarial Network (GAN)
A neural network framework that can generate new data.
Germany
Germany is known for its automotive industry and industrial machinery.
Graphene
Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.
The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.
Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2â
Vâ1â
sâ1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.
While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.
Graphics Double Data Rate (GDDR)
Graphics Processing Unit (GPU)
An electronic circuit designed to handle graphics and video.
Guard Banding
Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.
Hard IP
Fully designed hardware IP block
Hardware Assisted Verification
Use of special purpose hardware to accelerate verification
Hardware Modeler
Historical solution that used real chips in the simulation process
hardware/software co-design
Optimizing the design by using a single language to describe hardware and software.
Heat Dissipation
Power creates heat and heat affects power
Heterogeneous Integration
The process of integrating different chips, chiplets, and chip components into packages.
High-Bandwidth Memory (HBM)
A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.
High-Density Advanced Packaging (HDAP)
An umbrella term (circa 2015) for advanced packaging in semiconductors.
High-Level Synthesis (HLS)
Synthesis technology that transforms an untimed behavioral description into RTL
HSA Platform System Architecture Specification
Defines a set of functionality and features for HSA hardware
HSA Runtime Programmerâs Reference Manual
Runtime capabilities for the HSA architecture
Hybrid Bonding
IC Types
What are the types of integrated circuits?
IEEE 1076-VHSIC HW Description Language
Hardware Description Language
IEEE 1076.1-Analog & Mixed-Signal
Analog extensions to VHDL
IEEE 1076.1.1-VHDL-AMS Standard Packages
A collection of VHDL 1076.1 packages
IEEE 1076.4-VHDL Synthesis Package â Floating Point
Modeling of macro-cells in VHDL
IEEE 1149 Boundary Scan Test
Boundry Scan Test
IEEE 1364-Verilog
IEEE ratified version of Verilog
IEEE 1364.1-Verilog RTL Synthesis
Standard for Verilog Register Transfer Level Synthesis
IEEE 1532- in-system programmability (ISP)
Extension to 1149.1 for complex device programming
IEEE 1647-Functional Verification Language e
Functional verification language
IEEE 1666-Standard SystemC
SystemC
IEEE 1685-IP-XACT
Standard for integration of IP in System-on-Chip
IEEE 1687-IEEE Standard for Access and Control of Instrumentation Embedded
IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
IEEE 1800-SystemVerilog
IEEE ratified version of SystemVerilog
IEEE 1800.2âUVM
Universal Verification Methodology
IEEE 1801-Design/Verification of Low-Power, Energy-Aware UPF
IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)
IEEE 1838: Test Access Architecture for 3D Stacked IC
Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
IEEE 1850-Property Specification Language (PSL)
Verification language based on formal specification of behavior
IEEE 802.1-Higher Layer LAN Protocols
IEEE 802.1 is the standard and working group for higher layer LAN protocols.
IEEE 802.11-Wireless LAN
IEEE 802.11 working group manages the standards for wireless local area networks (LANs).
IEEE 802.15-Wireless Specialty Networks (WSN)
IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.
IEEE 802.18-Radio Regulatory TAG
"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.
IEEE 802.19-Wireless Coexistence
Standards for coexistence between wireless standards of unlicensed devices.
IEEE 802.3-Ethernet
IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.
IEEE P2415: Unified HW Abstraction & Layer for Energy Proportional Electronic Systems
Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
IEEE P2416-Power Modeling
Power Modeling Standard for Enabling System Level Analysis
IEEE-ISTO 5001 (Nexus 5001) â embedded processor debug
IIoT: Industrial Internet of Things
Specific requirements and special consideration for the Internet of Things within an Industrial setting.
Impact of lithography on wafer costs
Wafer costs across nodes
Implementation Power Optimizations
Power optimization techniques for physical implementation
In-Memory Computing
Performing functions directly in the fabric of memory.
Induced Gate Noise
Thermal noise within a channel
Insulated-Gate Bipolar Transistors (IGBT)
IGBTs are combinations of MOSFETs and bipolar transistors.
Integrated Circuits (ICs)
Integration of multiple devices onto a single piece of semiconductor
Integrated Device Manufacturer (IDM)
A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).
Intellectual Property (IP)
A design or verification unit that is pre-packed and available for licensing.
Inter Partes Review
Method to ascertain the validity of one or more claims of a patent
Interconnects
Interconnects (BEOL)
Buses, NoCs and other forms of connection between various elements in an integrated circuit.
Internet of Things (IoT)
Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.
Interposers
Fast, low-power inter-die conduits for 2.5D electrical signals.
Inverse Lithography Technology (ILT)
Finding ideal shapes to use on a photomask.
Ion Implants
Injection of critical dopants during the semiconductor manufacturing process.
IP-XACT
Standard for integration of IP in System-on-Chip
IR Drop
The voltage drop when current flows through a resistor.
ISO 21434 / SAE 21434 Standard â Automotive cybersecurity
ISO 26262 â Functional safety
Standard related to the safety of electrical and electronic systems within a car
ISO/PAS 21448 â SOTIF
Standard to ensure proper operation of automotive situational awareness systems.
ISO/SAE FDIS 21434-Road Vehicles â Cybersecurity Engineering
A standard (under development) for automotive cybersecurity.
Israel
Issues
Koomeyâs Law
The energy efficiency of computers doubles roughly every 18 months.
Languages
Languages are used to create models
Large Language Models (LLMs)
Laws
Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.
Layout versus Schematic Checking (LVS)
Device and connectivity comparisons between the layout and the schematic
Level Shifters
Cells used to match voltages across voltage islands
Line Edge Roughness (LER)
Deviation of a feature edge from ideal shape.
Lint
Removal of non-portable or suspicious code
Litho Etch Litho Etch (LELE)
LELE is a form of double patterning
Litho Freeze Litho Etch
A type of double patterning.
Lithography
Light used to transfer a pattern from a photomask onto a substrate.
Lithography k1 coefficient
Coefficient related to the difficulty of the lithography process
Logic Resizing
Correctly sizing logic elements
Logic Restructuring
Restructuring of logic for power reduction
Logic Simulation
A simulator is a software process used to execute a model of hardware
Low Power Double Data Rate (LPDDR)
Low Power Methodologies
Methodologies used to reduce power consumption.
Low Power Verification
Verification of power circuitry
Low-Power Design
Machine Learning (ML)
An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.
Magnetoresistive RAM (MRAM)
Uses magnetic properties to store data
Makimotoâs Wave
Observation related to the amount of custom and standard content in electronics.
Manufacturing Execution System (MES)
Tracking a wafer through the fab.
Manufacturing Noise
Noise sources in manufacturing
Materials
Semiconductor materials enable electronic circuits to be constructed.
Memory
A semiconductor device capable of retaining state information for a defined period of time.
MEMS
Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.
Metal Organic Chemical Vapor Deposition (MOCVD)
A key tool for LED production.
Metastability
Unstable state within a latch
Metcalfeâs Law
Observation that relates network value being proportional to the square of users
Methodologies and Flows
Describes the process to create a product
Metrology
Metrology is the science of measuring and characterizing tiny structures and materials.
Microcontroller (MCU)
A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.
Microprocessor, Microprocessor Unit (MPU)
The integrated circuit that first put a central processing unit on one chip of silicon.
Mixed-Signal
The integration of analog and digital.
Models
Models and Abstractions
Models are abstractions of devices
Molded Interconnect Substrate (MIS)
A midrange packaging option that offers lower density than fan-outs.
Monolithic 3D Chips
A way of stacking transistors inside a single chip instead of a package.
Mooreâs Law
Observation related to the growth of semiconductors by Gordon Moore.
Multi-Beam e-Beam Lithography
An advanced form of e-beam lithography
Multi-chip Modules (MCM)
An early approach to bundling multiple functions into a single package.
Multi-Corner Multi-Mode (MCMM) Analysis
Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
Multi-Die Assemblies
Multi-site testing
Using a tester to test multiple dies at the same time.
Multi-Vt
Use of multi-threshold voltage devices
Multiple Patterning
A way to image IC designs at 20nm and below.
Nanoimprint Lithography
A hot embossing process type of lithography.
Nanosheet FET
A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.
Near Threshold Computing
Optimizing power by computing below the minimum operating voltage.
Near-Memory Computing
Moving compute closer to memory to reduce access costs.
Negative Bias Temperature Instability (NBTI)
NBTI is a shift in threshold voltage with applied stress.
Network on Chip (NoC)
An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.
Neural Networks
A method of collecting data from the physical world that mimics the human brain.
Neuromorphic Computing
A compute architecture modeled on the human brain.
Nodes
Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.
Noise
Random fluctuations in voltage or current on a signal.
Non-Volatile Memory (NVM)
Memory in which information is retained even when a power source is not present.
Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1
NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and whatâs being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.
Fundamentally, there are two types of NVM:
Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.
Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.
Then thereâs the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, itâs difficult to do it because the oxide thickness is not there to do to make it happen.
However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.
The OTP technology doesnât require the thicker oxide that is required for the MTP, and there is no floating gate.
1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/
Open Verification Methodology (OVM)
Verification methodology created from URM and AVM
Operand Isolation
Disabling datapath computation when not enabled
Optical Inspection
Method used to find defects on a wafer.
Optical Lithography
Optical Proximity Correction (OPC)
A way to improve wafer printability by modifying mask patterns.
Original Equipment Manufacturer (OEM)
The company that buys raw goods, including electronics and chips, to make a product.
Outsourced Semiconductor Assembly and Test (OSAT)
Companies who perform IC packaging and testing - often referred to as OSAT
Overlay
The ability of a lithography scanner to align and print various layers accurately on top of each other.
package-on-package (PoP)
Packaging
How semiconductors get assembled and packaged.
Part Average Testing (PAT)
Outlier detection for a single measurement, a requirement for automotive electronics.
Patterning
PCI Express (PCIe), Peripheral Component Interconnect Express
High-speed serial expansion bus for connecting sending data between devices.
Pellicle
A thin membrane that prevents a photomask from being contaminated.
Phase-Change Memory
Memory that stores information in the amorphous and crystalline phases.
Photomask
A template of what will be printed on a wafer.
Photonic Integrated Circuit (PIC)
Photonics
Photoresist
Light-sensitive material used to form a pattern on the substrate.
Physical AI
Physical Design
Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.
Physical Layer (PHY)
Physically connects devices and is the conduit that encodes, decodes bits of data.
Physical Vapor Deposition (PVD)
PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.
Physical Verification
Making sure a design layout works as intended.
Physically Unclonable Functions (PUFs)
A set of unique features that can be built into a chip but not cloned.
Pin Swapping
Lowering capacitive loads on logic
Planar
PODEM
An algorithm used ATPG
Portable Stimulus (PSS)
Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.
Power
Power Consumption
Components of power consumption
Power Cycle Sequencing
Power domain shutdown and startup
Power Definitions
Definitions of terms related to power
Power Delivery Network (PDN)
Moving power around a device.
Power Estimation
How is power consumption estimated
Power Gating
Reducing power by turning off parts of a design
Power Gating Retention
Special flop or latch used to retain the state of the cell when its main power supply is shut off.
Power Isolation
Addition of isolation cells around power islands
Power Issues
Power reduction at the architectural level
Power Management Coverage
Ensuring power control circuitry is fully verified
Power Management IC (PMIC)
An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.
Power MOSFETs
A power semiconductor used to control and convert electric power.
Power Semiconductors
A power IC is used as a switch or rectifier in high voltage power applications.
Power Semiconductors Report: A Deep Dive Into Materials, Manufacturing & Business
Power Supply Noise
Noise transmitted through the power delivery network
Power Switching
Controlling power for power shutoff
Power Techniques
Power-Aware Design
Techniques that analyze and optimize power in a design
Power-Aware Test
Test considerations for low-power circuitry
PPA (Power, Performance, Area)
Fundamental tradeoffs made in semiconductor design for power, performance and area.
Printed Circuit Board (PCB)
The design, verification, assembly and test of printed circuit boards
Process
Process Power Optimizations
power optimization techniques at the process level
Process Variation
Variability in the semiconductor manufacturing process
Processor Utilization
A measurement of the amount of time processor core(s) are actively in use.
Processors
An integrated circuit or part of an IC that does logic and math processing.
Property Specification Language
Verification language based on formal specification of behavior
Quantum Computing
A different way of processing data using qubits.
Radio Frequency (RF)
Issues that pertain to Radio Frequency (RF) analog
Random Telegraph Noise
Random trapping of charge carriers
Rapid Thermal Anneal (RTA), Rapid Thermal Processing (RTP)
The process of rapidly heating wafers.
Redistribution Layers (RDLs)
Copper metal interconnects that electrically connect one part of a package to another.
Regional Developments/Issues
Reliability Verification
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.
ReRAM materials
Materials used to manufacture ReRAMs
Resistive RAM (ReRAM/RRAM)
Memory utilizing resistive hysteresis
Reticle
Synonymous with photomask.
Rich Interactive Test Database (RITdb)
A proposed test data standard aimed at reducing the burden for test engineers and test operations.
RISC-V
An open-source ISA used in designing integrated circuits at lower cost.
Root of Trust
Trusted environment for secure functions.
RTL (Register Transfer Level)
An abstraction for defining the digital portions of a design
RTL Power Optimizations
Optimization of power consumption at the Register Transfer Level
RTL Signoff
A series of requirements that must be met before moving past the RTL phase
RVM
Verification methodology based on Vera
SAT Solver
Algorithm used to solve problems
Scan Test
Additional logic that connects registers into a shift register or scan chain for increased test efficiency.
Scoreboard
Mechanism for storing stimulus in testbench
SCV SystemC Verification
Testbench support for SystemC
Self-Aligned Double Patterning (SADP)
A form of double patterning.
Semiconductor Manufacturing
Subjects related to the manufacture of semiconductors
Semiconductor Security
Methods and technologies for keeping data safe.
Sensor Fusion
Combining input from multiple sensor types.
Sensor Signal Conditioner (SSC)
An IC that conditions an analog sensor signal and converts to it digital before sending to a microcontroller.
Sensors
Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.
serializer/deserializer (SerDes)
A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.
Shift Left
In semiconductor development flow, tasks once performed sequentially must now be done concurrently.
Shmooing, Shmoo test, Shmoo plot
Sweeping a test condition parameter through a range and obtaining a plot of the results.
Short Channel Effects
When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.
Shot Noise
Quantization noise
Side Channel Attacks
A class of attacks on a device and its contents by analyzing information using different access methods.
Silent Data Corruption (SDC)
Undetected errors in data output from an integrated circuit.
Silicon Carbide (SiC)
A wide-bandgap technology used for FETs and MOSFETs for power transistors.
Silicon Photonics
The integration of photonic devices into silicon
Simulation
A simulator exercises of model of hardware
Simulation Acceleration
Special purpose hardware used to accelerate the simulation process.
Simultaneous Switching Noise
Disturbance in ground voltage
Small Language Models (SLMs)
Soft IP
Synthesizable IP block
Software-Defined Vehicles (SDV)
Software-Driven Verification
Verification methodology utilizing embedded processors
Software/Hardware Interface for Multicore/Manycore (SHIM) processors
Defines an architecture description useful for software design
SPICE
Circuit Simulator first developed in the 70s
Spiking Neural Network (SNN)
A type of neural network that attempts to more closely model the brain.
Spin-Orbit Torque MRAM (SOT-MRAM)
A type of MRAM with separate paths for write and read.
Standard Essential Patent
A patent that has been deemed necessary to implement a standard.
Standard Test Data Format (STDF)
The most commonly used data format for semiconductor test information.
Standards
Standards are important in any industry.
Standards & Laws
Startup Funding in China eBook: Notable investments in the semiconductor industry
Startups
Static Random Access Memory (SRAM)
SRAM is a volatile memory that does not require refresh
Stimulus Constraints
Constraints on the input to guide random generation process
Stochastics, Stochastic-Induced Defects
Random variables that cause defects on chips during EUV lithography.
STT-MRAM
An advanced type of MRAM
Substrate Biasing
Use of Substrate Biasing
Substrate Noise
Coupling through the substrate.
System In Package (SiP)
A method for bundling multiple ICs to work together as a single chip.
System on Chip (SoC)
A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor
SystemC
A class library built on top of the C++ language used for modeling hardware
SystemC-AMS
Analog and mixed-signal extensions to SystemC
SystemVerilog
Industry standard design and verification language
Tensor Processing Unit (TPU)
Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.
Testbench
Software used to functionally verify a design
Thermal Noise
Noise related to heat
Through-Silicon Vias (TSVs)
Through-Silicon Vias are a technology to connect various die in a stacked die configuration.
Trace
Transistors
Basic building block for both analog and digital integrated circuits.
Transition Rate Buffering
Minimizing switching times
Triple Patterning
A multi-patterning technique that will be required at 10nm and below.
Tunnel FET
A type of transistor under development that could replace finFETs in future process technologies.
UL 4600 â Standard for Safety for the Evaluation of Autonomous Products
Standard for safety analysis and evaluation of autonomous vehicles.
Unified Coverage Interoperability Standard (Verification)
The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.
Unified Power Format (UPF)
Accellera Unified Power Format (UPF)
Universal Chiplet Interconnect Express (UCIe)
Die-to-die interconnect specification.
Universal Verification Methodology (UVM)
Verification methodology
URM
SystemVerilog version of eRM
User Interfaces
User interfaces is the conduit a human uses to communicate with an electronics device.
Utility Patent
Patent to protect an invention
Vera
Hardware Verification Language
Verification
Verification IP (VIP)
A pre-packaged set of code used for verification.
Verification Methodologies
A standardized way to verify integrated circuit designs.
Verification Plan
A document that defines what functional verification is going to be performed
Verilog
Hardware Description Language in use since 1984
Verilog Procedural Interface
Procedural access to Verilog objects
Verilog-AMS
Analog extensions to Verilog
VHDL
Hardware Description Language
Virtual Prototype
An abstract model of a hardware system enabling early software execution.
VMM
Verification methodology built by Synopsys
Voice control, speech recognition, voice-user interface (VUI)
Using voice/speech for device command and control.
Volatile Memory
Memory that loses storage abilities when power is removed.
Voltage Islands
Use of multiple voltages for power reduction
Von Neumann Architecture
The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.
Wafer Fab Testing
Verifying and testing the dies on the wafer after the manufacturing.
Wafer Inspection
The science of finding defects on a silicon wafer.
Wi-Fi
A brand name for a group of wireless networking protocols and technology,
Wide I/O: memory interface standard for 3D IC
3D memory interface standard
Wirebonding
Creating interconnects between IC and package using a thin wire.
Wireless
A way of moving data without wires.
X Architecture
IC interconnect architecture
X Verification
X Propagation causes problems
Yield Management System (YMS)
A data-driven system for monitoring and improving IC yield and reliability.
Zero-Day Vulnerabilities, Attacks
A vulnerability in a productâs hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.
Zonal Architectures
Aart de Geus
Adam Kablanian
Aditya Mittal
Adnan Hamid
Adrian Simionescu
Ahmed Hemani
Ajay Daga
Ajoy K. Bose
Akash Deshpande
Aki Fujimura
Al Akermann
Alain Fanet
Alain J. Hanover
Alakesh Chetia
Alan Scott
Alberto Sangiovanni-Vincentelli
Alex Alexanian
Alexander Samoylov
Alisa Yaffa
Allan Douglas
Amir Zarkesh
Amit Gupta
Amit Mehrotra
Amit Narayan
Amit Saxena
Amr Mohsen
An-Chang Deng
An-Yu Kuo
Anant Agarwal
AndrĂĄs Poppe
Andrea Casotto
Andreas Ripp
Andreas Veneris
Andrei Tcherniaev
Andrew Hughes
Andrew T. Yang
Andrzej Strojwas
Andy Chou
Andy Goodrich
Andy Huang
Andy Ladd
Andy Lin
Ange Aznar
Anmol Mathur
Anupam Bakshi
Apo Sezginer
Apostolos Liapist
Aram Mirkazemi
Ari Takanen
Armin Biere
Arnaud Schleich
Arul Sharan
Arvind Mithal
Aryeh Finegold
Asen Asenov
Ashawna Hailey
Ashraf Takla
Asoke K. Laha
Atsushi Kasuya
Atul Bhagat
Atul Bhatia
Aurangzeb Khan
Avideh Zakhor
Avishai Silvershatz
Axel Jantsch
Babu Chilukuri
Badru Agarwala
Barry Katz
Barry Rosales
Bart De Smedt
Becky Cavanaugh
Ben Chelf
Ben Levine
Bendt Sorensen
Bernard Vonderschmitt
Bernie Rosenthal
Bill Berg
Bill Buckie
Bill Childs
Bill Hoover
Bill Krieger
Bill Neifert
Bill Robertson
Bill Sommer
Biman Chattopadhyay
Bing Yeh
Bob Flatt
Bob Hunter
Bob Quinn
Borgar Ljosland
Boris Gruzman
Brad Quinton
Brian Davenpoort
Bruce M. Holland
Bryan Hoyer
Carson Bradbury
Carver Mead
CĂŠsar Douady
Char Devich
Charles Edelstenne
Charles Evans
Charles J. (Chuck) Abronson
Charlie Cheng
Charlie Huang
Cheng Wang
Chenming Hu
Chi-Lai Huang
Ching-Chao Huang
Chioumin (Michael) Chang
Chong Ming (Frank) Lin
Chouki Aktouf
Chris Schalick
Chris Wilson
Chris Curry
Chris Rosebrugh
Chris Rowen
Christian Masson
Christophe Alexandre
Chung-Kuan Cheng
Claes StrannegĂĽrd
Claudio Basile
Cleve Moler
Clifton (Cliff) Lyons
Clinton W. Kelly
Coby Zelnik
Colin Hunter
Craig Harris
Craig Honegger
Craig Gleason
Craig Stoops
Cristian Amitroaie
Cyril Spasevski
Cyrus Afghahi
Da Chuang
Damian Smith
Dan Abrams
Dan Chapiro
Dan Jaskolski
Dan Malek
Danesh Tavana
Daniel Hansson
Dave Gregory
Dave Millman
Dave Moffenbeier
David Marple
David Botting
David Chyan
David Coelho
David E. Long
David Galloway
David Greaves
David Hamilton
David Henke
David Johannsen
David Novosel
David Overhauser
David Park
David Pellerin
David R. Stevens
David Stamm
David Stewart
David Yao
Davorin Mista
Dawson Engler
Dean Drako
Deepak Shankar
Deepak Kumar Tala
Dejan Markovic
Derek King
Devadas Varma
Devesh Guatam
Diana Marculescu
Dirk Lanneer
Dominik Strasser
Don Emil Pezzolo
Don McInnis
Don-Min Tsou
Donald Bennett
Doug Fairbairn
Drew E. Wingard
Duncan Bremner
Durga Lakshmi Sangisetti
Ed Blackmond
Edmund K. Cheng
Edvard Sørgürd
Edward A. Lee
Edward Komp
Edward N. Evans
Egino Sarto
Elena Potanina
Eli Yablonovitch
Ellis Smith
Enno Wein
Eric Ryherd
Eric Beisser
Eric Dormer
Eric Dupont
Eric Dupont-Nivet
Eric Peers
Eric T. Hennenhoefer
Erik Lauwers
Esin Terzioglu
Eun Sei Park
Ewald Detjens
Fadil Kotaji
Fang-Cheng Chang
Fang-Li Yuan
Farakh Javid
Fergus Slorach
Fia Johansson
Firas Mohamed
Founder(s) Unknown
François Constant
Francis Bernard
Frank Gennari
Frank Costa
Frank DeRemer
Frank Schenkel
Franz Dugand
Frederic Reblewski
Frederick (Fred) Saal
Fuad Musa
Fumiaki Sato
Gabi Leshem
Gagan Hasteer
Ganapathy Subramaniam
Gene Dancause
Gene Marsh
Geoffrey Tate
Gerald H. Langeler
Gerald L (Jerry) Frenkil
Gerald Pechanek
Gerhard Angst
Gert Goossens
Ghassan (Gus) Y. Yacoub
Ghislain Kaiser
Giacinto Paolo Saggese
Gil Winograd
Glen M. Antle
Gopa Periyadan
Gopal Krishna Nayak
Gordon B. Hoffman
Gordon Baty
Gordon E. Moore
Graham Hellestrand
Grant A. Pierce
Greg Doyle
Greg Hoeppner
Greg Lloyd
Greg M. Ordy
Gregory Recupero
Guido Arnout
GĂźnter Keil
Guy Bois
Guy de Burgh
Hal Alles
Hal Conklin
Hamid Savoj
Harald Neubauer
Hardeep Gulati
Harm Arts
HarnHua Ng
Harvey C. Jones jr.
Hayder Mrabet
Hazem El Tahawy
Hein van der Wildt
Heinrich Meyr
Helmut Gräb
Helmut Mahr
Henrik Pallisgaard
Henry Cox
Hermann Hauser
Hiro Moriyasu
Holly Stump
Howard L. Martin
Howard Pakosh
Ian Lankshear
Ian Page
Ian Tsybulkin
Ihao Chen
Ivan Pesic
J. Eric Bracken
J. George Janac
Jack Herrick
Jack Harding
Jack Little
Jack Peng
Jacob Ben-Meir
James (Jim) Fiske
James (Jim) Ready
James B. Morris
James C. Rautio
James E. (Jim) Solomon
James G. Crocker
James Girand
James Truchard
James V Barnett II
Jamsheed Agahi
Janak H. Patel
Jane Karwoski McCracken
Jason Campbell
Jason Cong
Jason Xing
Jauher Zaidi
Jaushin Lee
Jay Avula
Jean Barbier
Jean Brouwers
Jean-Luc Pelloie
Jean-Philippe Lambert
Jean-Pierre Appel
Jean-Pierre Lecailliez
Jean-Yves Brena
Jeff Fox
Jeff Bier
Jeff Galloway
Jeff Kodosky
Jeff Tuan
Jens C. Michelsen
Jens J. Tybo Jensen
Jens P. Tagore-Brage
Jeong-Tyng Li
Jeremy Birch
Jerome Vanthournout
Jesper Knudsen
Jez San
Jian X. Zheng
Jim McCanny
Jim Sansbury
Jinsong Zhao
Joe Higgins
Joe Tanous
Joe Tatham
Joerg Grosse
Joey Y. Lin
Johan Van Praet
Johan Peeters
Johann Foucher
Johannes Emigholz
John Gilbert
John A. Swanson
John Charles Carveth
John Croix
John Durbetaki
John F. Cooper
John Goodenough
John Halfpenny
John Hall
John Hatfield
john Judkins
John K. Kibarian
John Lee
John Lofton Holt
John Maneatis
John Mills
John Ott
John R. Maticich
John Sanguinetti
John Tanner
Johnathan Weiss
Johnson Limqueco
Jonathan Cagan
Jonathan Rose
Jordan Swartz
Joseph Skazinski
Joseph B. Costello
Joseph E. Pekarek
Joseph Lee
Joseph Rothman
Josh Lee
Juliusz Poltz
Jun-Jyeh Hsiao
Jørn Nystad
K. Charles Janac
K.C. Shih
Kaiwin Lee
Kamran Elahian
Kannankote Sriram
Karel Masarik
Karen Vahtra
Kaushik I. Sheth
Kavitha Tala
Keith Short
Keith Seymour
Keith Whisnant
Ken McElvain
Ken Matusow
Ken Seymour
Ken Tseng
Kenneth L. Shepard
Kevin Chou
Kevin Hotaling
Kevin Ladd
Khalil Shalish
Kim Hailey
Kimon Michaels
Kirvy Teo
Kurt Matis
L. Curtis Widdoes Jr.
L. John Doerr III
L. Richard Carley
Larry Carver
Larry Lewis
Larry Rubin
Lars-Eric Lundgren
Laurent Moss
Laurent RougĂŠ
Lawrence T. (Larry) Pileggi
Lee Tavrow
Lei He
Lev A. Markov
Limin He
Lip-Bu Tan
Lisa McIlrath
Lloyd Pople
Lothar Linhard
Luc Burgun
Lucio Lanza
Lukas van Ginneken
Lutz P. Henckles
Maha Zaidi
Maheen Hamid
Mahesh Rao
Mahshad Koohgoli
Manny Marcano
Mar Hershenson
Marc Renaudin
Marc Witteman
Marcelino Santos
Marco Rubinstein
Margarida Sousa
Margie Levine
Mario Blazevic
Mark Beardslee
Mark Cianfaglione
Mark Hampton
Mark Horowitz
Mark OâDonovan
Mark Olen
Mark R. Templeton
Mark Santoro
Mark Waller
Mark Williams
Mark-Eric Jones
Markus Mergens
Marleen Boonen
Martin Baechtold
Martin Langhammer
Martin Lefebvre
Martin Walker
Martin Wilson
Mathias Silvant
Maurice Whelan
Maurizio Arienzo
Maximilian Odendahl
Mehmet A. Cirit
Mel Gilmore
Michael McNamara
Michael Alam
Michael Burstein
Michael D. Hoyt
Michael Goldstone
Michael J. Jamiolkowski
Michael Magranet
Michael Nicolaidis
Michael Pronath
Michael Wakim
Michel Oger
Mike Rieger
Mike Bartley
Mike Borza
Mike Chandler
Mike Dini
Mike Farmwald
Mike Kliment
Mike Lee
Mike Meredith
Mike Scase
Mike Yungho Tsai
Mikko Varpiola
Milton R. Smith
Misha Burich
Mohamed Kassem
Mohan R
Mojy Chian
Morris Chang
Murat Alaybeyi
Mustafa Celik
Naeem Zafar
Nagesh Gupta
Naveed Sherwani
Naveen Chava
Neil Johnson
Neil Roberts
Nick Cobb
Nick Martin
Nick Martin
Nicky Lu
Nicolas Delorme
Ning Nan
Noah Sturcken
Norman Chang
Ole Christian Andersen
Olivier Lepape
Ori Braun
Oscar Buset
P.T. Patel
Pascal Peru
Patrick J. Ready
Paul Cunningham
Paul (Yen-Son) Huang
Paul de Dood
Paul Harvell
Paul Johnson
Paul Levine
Paul Lindermann
Paul M. Hubbard
Paul Newhagen
Paul Nguon
Paul Rodman
Paul van Besouw
Paul Wells
Peer Schmitt
Pengwei Qian
Pete Popov
Peter Eichenberger
Peter Denyer
Peter Flake
Peter Ivey
Peter Meuris
Peter Odryna
Peter Petrov
Peter Rip
Petro Estakhri
Phil Moorby
Phil Tharp
Philippe Boucard
Philippe Diehl
Philippe Duchene
Pierre Marty
Prab Varma
Prabhat Aggarwal
Prabhu Goel
Pradeep Fernandes
Pradeep Vajram
Prakash Narain
Pravin Madhani
R. Dean Adams
R. Mark Gogolewski
R.K. Patil
Raghavendra Mohan V
Raik Brinkmann
Raj Raghavan
Rajeev Madhavan
Rajendran (Raj) Nair
Rajit Manohar
Rajit Chandra
Rajiv Kumar
Ralf Huuck
Ram S. Ramanujam
Ramin Hojati
Ramy Iskander
Randy Eager
Randy Allen
Randy Caplan
Randy Deffert
Randy Rhea
Raul Camposano
Rauli Kaksonen
Ravender Goyal
Ravi Mehta
Ravi Shankar Rao
Ravi Thummarukudy
Ray Bulgar
Raymond Turin
Reinhard Keil
RĂŠmi Butaud
Rhonda Dirvin
Rich Witek
Richard C. (Dick) Foss
Richard Chang
Richard Doherty
Richard Meacham
Richard Rudell
Richard Taylor
Richard Weber
Rick Carlson
Rick Lazansky
Rob A. Rutenbar
Rob Dekker
Rob Gowin
Robert Harland
Robert Kurshan
Robert Blackburn
Robert H. Dennard
Robert Hartmann
Robert Noyce
Robert Smith
Robi Dutta
Roger Sturgeon
Roger Gook
Ron Maxwell
Ronald A. Rohrer
Ross Feeman
Roy Prasad
Sagar Reddy
Sailesh Kumar
Sally Shlaer
Salvatore Carcia
Sam Appleton
Sam Kim
Samir Shroff
Sandeep Srinivasan
Sandipan Bhanot
Sang S. Wang
Sanjay Mittal
Sanjay K Srivastava
Sarang Padalkar
Satish Bagalkotkar
Satish Padmanabhan
Satya Gupta
Scott R. Powell
Scott T. Becker
Scott W. Houghton
Sean Safarpour
Serge Maginot
Seth Hallem
Shahram Besharati
Shail Aditya
Shajid Thiruvathodi
Shane Flint
Sharad Kapur
Shay Ben-Chorin
Shay Mizrachi
Shen Lin
Sherif Eid
Shiv Sikand
Shiv Tasker
Shubhodeep Roy Choudhury
Simon Butler
Simon Davidmann
Simon Garrison
Simon N. Springall
Snehanshu Shah
Soo-Young Oh
Sotiris Bantast
Srikanth Jadcherla
Srinath Anantharaman
Srinivasan Durai
Stanislav Ruev
Stanley M. Hyduke
Stanley Osher
Stanley Yang
Stefan Birman
Stephane Hauradou
StĂŠphane Leclercq
Stephen Crosher
Stephen Fairbanks
Stephen J. Mellor
Steve Teig
Steve Bangert
Steve Barlow
Steve Carlson
Steve Sapiro
Steve Walsh
Steve White
Steve Wilcox
Steve Yang
Steven Heinz
Steven LâHer
Steven Wang
Sudhir Kadkade
Sue Kunz
Sujoy Chakravarty
Sundar Iyer
Sundari Mitra
Sunil Jain
Sunil Samel
Sunil Talwar
Sycon Zohar
Sydney Lovely
Sylvian Kaiser
Tabor Smith
Tae Hoon Song
Tak Shigihara
Takis Breyiannis
Tallis Blalack
Tapan Joshi
Tarak Parikh
Taylor Scanlon
Terry Brewer
Thomas Kailath
Thomas Niermann
Thomas Schultz
Tim Haynes
Tobias Bjerregaard
Todd Masey
Tom Paddock
Tom Bruggere
Tom Cesear
Tom Harris
Tom McWilliams
Tom Quarles
Tony Curzon-Price
Toshio Nakama
Trent McClements
Trent McConaghy
Uma Bondada
Uri Tal
Vahagn Poghosyan
Vaughn Betz
Venkat Iyer
Venugopal Kolathur
Victor Savenko
Vigyan Singhal
Vikram Jandhyala
Vincent Perrier
Vincent Thibaut
Vinod K. Agarwal
Vinod Kathail
Vinod Narayanan
Virantha N. Ekanayake
Vishal Moondhra
Vivek Raghavan
Vivek Bhat
Vivek Pawar
Vlad Potanin
Vladimir Schellbach
Vojin Zivojnovic
Wai Yan (William) Ho
Walden (Wally) Rhines
Wally Haas
Walter Chan
Walter Daems
Warren Savage
Wayne Dai
Wayne Marking
Weihua Sheng
Weiping (Peter) Shi
Weize Xie
Werner Geurts
Will Herman
Willem vanCleemput
Willi Brandenburg
William âBillâ Billowitch
Wim Schoenmaker
Wim Verhaegen
Wlodek Kurjanowicz
Wojciech Sakowski
Wolfram BĂźttner
Wu-Tung Cheng
WĹodzimierz Wrona
Xerxes Wania
Xisheng Zhang
Xuequn (Kevin) Xiang
Yao-Ting Wang
Yi (Bob) Xu
Yoav Hollander
Yorgos Koutsoyannopoulost
Youn-Long (Steve) Lin
Yuan Lu
Yunshan Zhu
Yuri Feinberg
Z.M Simon Li
Zhihong Liu
Zhonghai Lu
Zied Marrakchi
Zvi Or-Bach
0-In Design Automation Inc.
3Soft Corporation
@HDL
Aachen University of Technology
ACAD Corp
Accel Technologies Inc.
Accelerant Networks, Inc.
Accelerated Technology (UK) Ltd.
Accelerated Technology Inc.
Accelicon Technologies
Accellera
Accellera Systems Initiative
Accellera UCIS WG
Accent S.R.L
Accolade Design Automation
ACEO Technology
Achronix Semiconductor Corporation
Acorn Computer Group
Actel Corp.
Adapt IP
ADAS Software
Adelante Technology
Adesto Technologies Corp.
Adicsys
Advanced CAM Technologies, Inc.
Advanced Micro Devices (AMD)
Advanced Microelectronics
Advanced RISC Machines Ltd.
Advanced Technology Center
Advanced Test Technology, Inc.
Advantest Corporation
AGGIOS, Inc.
Agilent EEsof EDA
Agilent Technologies
Agility Design Solutions
Agnisys, Inc.
Alarity Corporation
Alchemy Semiconductor
Aldec, Inc.
Algotochip Corporation
Allant Software
Allegro DVT
Alphabit
Alphawave Semi
Alta Group of Cadence
Altera Corporation
Altium, Inc.
Altius Solutions Inc.
Altos Design Automation, Inc.
Ambit Design Systems, Inc.
AMIQ EDA
Amkor Technology
AMS AG
Anacad Electrical Engineering Software GmbH
Anagram Inc.
Analog Bits Inc.
Analog Design Automation, Inc.
Analog Design Tools Inc.
Analogy Inc.
Anasim
Andes Technology
Andes Technology Corp.
Ansys
Antares
Antrim Design Systems Inc.
Apache Design Solutions, Inc.
Apical Ltd.
APLAC Solutions Corp.
Aplus Design Technologies Inc.
Applied Materials, Inc.
Applied Simulation Technology
Applied Wave Research, Inc.
Apres Technologies
Apteq Design Systems Inc.
Aptix Corporation
Arasan Chip Systems
ARC International PLC
Arcad SA
Arcadia Innovation, Inc.
Archer Systems
ArchPro Design Automation, Inc.
ArcSys Inc.
Arexsys S.A.
Argon Design Ltd.
Aristo Technology, Inc.
Arithmatica
Arium
Arkos Design Systems
Arkos Emulation Unit
Arm
Arrow Devices Pvt. Ltd.
ARS Microsystems Ltd.
Arteris
Artisan Components, Inc.
ASE (Advanced Semiconductor Engineering)
ASML
Aspec Technology Inc
ASSET InterTech
ASTC
Astronics Test Systems
Asygn
Atair GmbH
AtaiTec Corp.
ATEEDA Ltd.
Atlantic Aerospace Electronics Corp.
ATopTech
Atrenta, Inc.
Ausdia, Inc.
AutoESL Design Technologies, Inc.
Automated Integrated Design Systems
Automated Systems, Inc.
Automatic Parallel Designs
Automotive Electronics Council (AEC)
Avalon Microelectronics Inc.
Avant! Corporation
Averant, Inc.
AverStar
Avery Design Systems
Award Software
Axiom Daterer Skandinavien AB
Axiom Design Automation
Axiomise
Axis Systems, Inc.
AXYS Design Automation, Inc.
Azuro, Inc.
A|RT Technology of Adelante
Baya Systems
BDTI
Beach Solutions
Bell Labs DA group of Lucent
Benelux B.V
Berkeley Design Automation, Inc.
BlazeDFM
Blue Cheetah
Blue Pearl Software, Inc.
Bluespec, Inc.
BOPS, Inc.
Boulder Creek Engineering
Brandenburg GmbH
Breker Verification Systems
Brewer Science
Bridges2Silicon, Inc.
Brite Semiconductor
Broadcom
Bruker
BTA Technology
BTA Ultima Inc.
C Level Design, Inc.
C2 Design Automation
CAD Framework Initiative
Cadabra Design Automation, Inc.
Cadence 802.11 wireless LAN IP
Cadence Design Foundry
Cadence Design Systems
Cadence PANTA IP cores
Cadis GmbH
CADIX Corporation
CADIX ECAD division
CadMOS Design Technology, Inc.
Cadnetix Corporation
CAE systems
CAE Technology Inc.
Caeco Inc.
Caedent Corporation
Caetek Inc.
California Design Automation, Inc.
Calma Company
Calypto Design Systems, Inc.
Carbon Design Systems
CARDtools Systems
Carnegie Mellon University
Cascade Semiconductor Solutions, Inc.
CAST, Inc.
Catalytic Inc.
Catapult C Product Division
CEA
CEA-Leti
Celestry Design Technologies Inc.
Celoxica Holding Plc.
Certess Inc.
Certus Semiconductor
CEVA
CheckLogic Systems inc.
Chip & Chip, Inc.
Chip Estimate Corp
Chip Path Design Systems
ChipAgents
CHIPit business unit
ChipStart LLC
Chronologic Simulation
Chronology Inc.
Chrysalis Symbolic Design, Inc.
CIDA Technology, Inc.
CIM-Team GmbH
CiraNova Inc.
Clear Shape Technologies
Cliosoft, Inc.
CLK Computer-Aided Design, Inc.
CLK Design Automation, Inc.
Co-Design Automation, Inc.
Codasip Ltd.
Codefast, Inc
Codenomicon Oy
CodeSourcery Inc.
CoFluent Design
Cohu Inc.
Comdisco Systems Inc.
ComLSI
Compact Model Coalition
Compass Design Automation
Compiled Designs GmbH
Computer Simulation Technology GmbH
Computervision, Inc.
Computing-Tabulating-Recording Company
Concept Engineering GmbH
Context Corporation
Contour Design Systems, Inc.
Conversant Intellectual Property Management
Cooper and Chyan Technology Inc.
Cortus S.A.S.
Cosmic Circuits
CoSoft Ltd.
Council of EDA Standards Committee
Coventor, a Lam Research Company
CoverMeter Tool
CoWare LLC
Coyote Systems
Cre8 Ventures
Credence Systems Corporation
Critical Blue
Crosslight Software, Inc.
CyberOptics, a Nordson Test & Inspection company
CycleC and other technology assets
Cycuity
Cynapps
D2S
Daisy Systems Corporation
Dassault Systèmes
Dasys
Data I/O
Datalink Far East, Ltd
Dazix
DDE-EDA A/S
Deerbrook Systems Inc.
Defacto Technologies
Defense Advanced Research Agency (DARPA)
DelSoft India Pvt. Ltd
DELTA Microelectronics
Denali Software, Inc.
Desantage Corporation
Descartes Automation Systems
Descon InformationsSysteme GmbH
Design Acceleration Inc.
DesignAdvance Systems Inc.
DesignPRO Inc.
DĂŠtente Technology, Inc.
Diablo Research Co. LLC
Digital Blocks
Dini Group
Docea Power
Dolphin Integration
Dorado Design Automation, Inc.
Doulos
dQdt, Inc.
DR YIELD
DRC:DA
DSM Technologies Inc.
DSP Division of Philips Semiconductor
Duolog Technologies Ltd.
DXCorr Design, Inc.
Dynamic Soft analysis Inc.
E-Z-CAD, Inc.
Eagle Design Automation
Eagleware, Inc.
Eagleware-Elanix
eASIC Corporation
eBeam Initiative
eBizAutomation Inc.
ECAD Inc.
Ăcole Polytechnique de MontrĂŠal
ECSI
EDA Systems
EDAC
EdXact SA
EEsof, Inc.
efabless.com
Elanix, Inc.
Electronic System Design Alliance
Eliyan
Elliptic Technologies
Elsip AB
EMA Design Automation
Embedded Alley Solutions
Embedded Performance Inc.
Embedded Solutions Limited
Embedded Vision Alliance
Emulation and Verification Engineering
Emulation division of Mitsui Bussan
EnSilica Ltd.
Entasys Design Inc.
EPIC Design Technology, Inc.
Escalade Corp.
eSilicon Corporation
ESL assets of Agility
ESL assets of Celoxica
Esperan Ltd.
eTop Design Automation
EuroMIPS Systems
European Design Center
European Microelectronics Academy
EV Group
Evans Analytical Group
Evatronix IP Design Business
Evatronix SA
EverCAD Corporation
Everest Design Automation, Inc.
Excellent Design Inc.
Excellicon Inc.
Exemplar Logic, Inc.
Eximius Design
Expedera
ExperTest
ExpertIO, Inc.
Expressive Systems
Extreme DA, Corp.
Fairchild Semiconductor
Falanx Microsystems AS
FEI â Knights Technology
FEI Company
Fenix Design Automation
Ferric Semiconductor Inc.
Fidus Systems Inc.
First Earth Ltd.
FishTail Design Automation, Inc.
Flex Logix Technologies, Inc.
Flexras Technologies SAS
Flomerics EM software
Flomerics Group PLC
Flometrics group Plc
Flowmaster Ltd.
FormFactor
Forte Design Systems
FPGA technology of Kilopass
Fractal Technologies
Fraunhofer IIS EAS
Freescale â Virtual Garage
Freescale Semiconductor
Frequency Technology
Frontier Design
Frontline Design Automation, Inc.
G-Analog Design Automation Ltd.
Galaxy Semiconductor
Gambit Automated Design, Inc.
Gatefield
GateRocket
Gateway Design Automation
Gear Design Solutions, Inc.
Gemini Design Technology Inc.
Genedax
Georgia Tech
Get2Chip Inc.
Giga Scale Integration Corporation
Global Semiconductor Alliance
Global Unichip Corp.
GlobalFoundries
Goanna Software Pty Ltd
Gold Standard Simulations Ltd.
Gradient DAâs electrothermal analysis technology
Gradient Design Automation
Green Mountain Computing Systems
Hammercores, Inc.
HARDI Electronics AB
Harness Software Group
Hd Lab, K.K.
HDAC Inc.
HDL Design House
Helic, Inc.
Helios Software Engineering Ltd.
Heterogeneous System Architecture (HSA) Foundation
Hewlett-Packard Company
HHB assets
HHB Softron Inc.
High Level Design Systems
HighIP Design Company
Hoschar AG
HP Labs
HPL Technologies, Inc.
Huins
Hunter and Ready
HyperLynx, Inc.
IBM
IBM â Altium group
IBM Foundry
IC Manage
ICScape, Inc.
ICUCOM Corporation
IEC
IEEE
IEEE 1800.2
IEEE DASC
IEEE SA
IKOS Systems, Inc.
Imagination Technologies
Imec
iMODL
Imperas Inc.
Impinj
impinj NVM IP
IMS
In-Chip Systems
INCASES Engineering GmbH
Incentia Design Systems
Independent Design Automation Companies
Infineon Technologies
Infiniscale
Infinite Designs Ltd.
Ingenuus Corporation
Ingot Systems
InnoLogic Systems, Inc.
Innotech Corporation
Innovative CAD Software, Inc.
Innoveda, Inc.
INRIA
inSilicon Corporation
InSpec Validation System
Instigate CJSC
Integrand Software
Integrated Measurements Systems, Inc.
Integrated Silicon Systems, Inc.
Integrated Systems Engineering AG
Integrity Engineering, Inc.
Intel Corp.
Intel PLD business
Intelligent Systems Japan, KK
Intento Design
Interconnectix Inc.
Interfaces Technical Committee
Intergraph Electronics
Intergraph Inc.
interHDL
Intermetrics
Intermetrics VHDL simulator
International Organization of Standards
Interra IT
InTime Software
Invarian, Inc.
Invarium, Inc.
Inventra
Inventure Inc.
Invionics Inc.
IOTA Technology Inc.
IPextreme, Inc.
iRoC Technologies SA
ISSC Technology Corporation
Japanese customers of Cadence software
Jasper Design Automation
Jazz Semiconductor, Inc.
JCET
Jedat Inc.
JEDEC
Juniper Networks, Inc.
K2 Technologies, Inc.
Kandou Bus
Keil
Keysight Technologies
Kilopass Technology Inc.
Kimotion Technologies
KLA
KLA-Tencor
Knowlent Corporation
Kozio, Inc.
L-3 Communications
Lam Research
Lattice Semiconductor
Leda Design, Inc.
Leda SA
Leuven Industrial Software Company
Library Technologies, Inc.
Lighthouse Design Automation, Inc.
Logic Automation, Inc.
Logic Modeling Corporation
Logic Modeling Systems Inc.
Logical Devices, Inc.
LogicVision, Inc.
Logipard AB
Looking Glass Studios
Lorentz Solution, Inc.
LSI Logic
Luminescent Mask Synthesis technology
Luminescent Technologies
Magillem
Magma Design Automation Inc.
Magwel NV
Marple Technologies
Marvell Technology
Massachusetts Institute of Technology
Massteck Ltd.
Mathtools Ltd
Mathworks
Maxim Integrated Inc.
Memory BIST Division of iRoC
Menta
Mentor Embedded Systems Division
Mentor Emulation Division
Mentor Mechanical Analysis Division
Mentor physical libraries
Mercel AB
Mercel AUTOSAR assets
Meropa Inc.
Meta Systems SARL
Meta-Software Inc.
Metamor Inc.
MetaWare Inc.
Methodics, Inc.
Micro Magic EDA assets
Micro Magic, Inc.
Microchip Technology, Inc.
Microcode Engineering Inc.
Microcosm Technologies Inc.
Microelectronics Research & Development Ltd.
Micrologic Solutions Limited
Microsemi Corporation
MicroSim Corp
Microtec Research, Inc.
Microtronic
Mint Technology
MIPI Alliance
MIPS Analog Business Group
MIPS Technologies
Mirabilis Design
Missing Link Tools
MITRE Engenuity
Mitsui Bussan Digital Corp
Mixel, Inc.
Mobiveil, Inc.
Model Technology Inc.
Modus Test
Mojave, Inc.
MonolithIC 3D Inc
Monterey Design Systems, Inc.
Moortec Semiconductor Ltd.
Morfik Technology Pty Ltd.
MOSAID SIP assets
MOSAID Technologies Inc.
Moscape, Inc
MOSIS
Mosys SerDes IP
MoSys, Inc.
Movellus
Multicore Association
MunEDA GmbH
NanGate, Inc.
Nannor Technologies Inc.
Nascentric, Inc.
Nassda Corporation
National Research Council of Canada
National Semiconducor
Neolinear, Inc.
NetSpeed Systems
Network Design Tools, Inc.
NeuroCAD Inc.
Nexsyn Design Technology Inc
Next Device Limited
NextOp Software, Inc.
NI (formerly National Instruments)
Nimbic, Inc.
NM Electronics
Northwest Logic, Inc.
Nova
Novarm Limited
Novas Software
Novelics
Novo Systems Corp
Novocell Semiconductor, Inc.
NP Komplete Technologies BV
nSys Design Systems Private Limited
Numerical Technologies, Inc.
NuPGA
Nusym Technology, Inc.
NXP CMOS IP
NXP Semiconductor
Oasys Design Systems Inc.
Obsidian Software
OCP-IP
Omnicad Corp.
OneSpin Solutions GmbH
Onto Innovation
OPC Technology
Open Networks Engineering
Open SystemC Initiative
Open Verilog International
Open Virtual Platforms
Open-Silicon, Inc.
OptEM Engineering Inc.
Optic2Connect Pte Ltd
Optical Internetworking Forum (OIF)
Optical Research Associates LLC
Optimal Corporation
Optimal Solutions, Inc.
OptimalPlus
OrCAD
Oski Technology
Out of Business
Pacer Infotec Inc.
PADS Software Inc.
Palmchip Corporation
Palmchip interface IP
Panel Level Packaging Consortium (PLC)
Paradigm Works
Parsec Software Inc.
PCB Libraries Inc.
PCB Matrix Corporation
PDF Solutions
Performance CAD
Performance Signal Integrity, Inc.
Performance-IP, LLC.
Personal CAD Systems
Pextra Corporation
Philips Semiconductor
Phoenix Technologies Ltd.
Physware, Inc.
PiE Design Systems Inc.
Pinebush Technologies
Plato Design Systems
PLDA
Pleiades Design and Test Technologies Inc.
Plunify Pte Ltd
Pollen Technology
PolySpace Technologies
Ponte Solutions Inc.
Portable Stimulus Working Group (PSWG)
PowerEscape, Inc.
Praesagus, Inc.
Precedence Inc.
Precim Corp
Precise Software Technologies Inc
ProDesign Electronic GmbH
Progressant Technologies, Inc.
Project Technology Inc.
Prolific, Inc.
Promex Industries
ProPlus Design Solutions, Inc.
ProSoft Oy
proteanTecs
Protecode
Protel International Pty, Ltd.
Provis Corporation
prpl foundation
Pulsic
Pyxis Technology
Q Design Automation
Q Point Technology
QP Technologies
QPX GmbH
Quad Design Technology, Inc.
Quadric
Quadtree Software Corporation
Qualcomm Incorporated
Qualis, Inc.
Quickturn Design Systems, Inc.
R3Logic, Inc.
Racal Redac
Racal Redac â VHDL simulator
Racal Redac SilcSyn
Radiant Design Tools, Inc.
Rambus, Inc.
Random Logic Corporation
RAPID
RaveSim, Inc.
RAVIcad Inc.
Ready Systems
Real Intent, Inc.
Redwood Design Automation
Renesas Electronics
ReShape Inc
RevoSys Inc.
Right Track CAD Corp.
Rio Design Automation
Riscure
RivieraWaves
Rocketick
Router Soutions, Inc.
Royal Digital Centers, Inc.
RSoft Design Group Inc.
Runtime Design Automation
S2C Inc.
S3 Group
Sabio Labs
Safelogic
Sagantec
Sage Design Automation, Inc.
Samsung Semiconductor
Sand Microelectronics
Sandburst
Sandwork Design, Inc.
Sankalp Semiconductor
SCALD Corporation
SciFace Software GmbH & Co. KG
SDA Systems Inc.
Sedco
See Technologies
Seed Solutions Inc.
SEMI
Semiconductor Manufacturing International Corp.
Semifore, Inc.
Sente Inc.
Sequence Design
SETO Software GmbH
Shiva Multisystems Corp.
Si2
Si2 Open3D Technical Advisory Board
Sibridge Technologies
SiCAD Inc.
Sidense Corp.
Siemens EDA
Sierra Design Automation
Sigma-C Software AG
Signal Integrity Software, Inc.
Signetics Corporation
Sigrity, Inc.
SilabTech Pvt Ltd.
Silc Technologies
Silerity Inc
Silexica
Silicon Architects
Silicon Canvas, Inc.
Silicon Cloud International Pte Ltd
Silicon Compiler Systems Corp.
Silicon Compilers Inc.
Silicon Creations, LLC
Silicon Design Labs
Silicon Design Solutions
Silicon Forest Research inc.
Silicon Frontline Technology, Inc.
Silicon Logic Engineering
Silicon Metrics Corporation
Silicon Perspective Corp.
Silicon Solutions Corporation
Silicon Sorcery
Silicon Storage Technology, Inc.
Silicon Valley Research
Silicon West
SiliconBlue Technologies Corporation
SiliconGate LDA
Siliconware Precision Industries
Silvaco, Inc.
Silvar-Lisco, Inc.
Simon Software
Simpleware
Simplex Solutions
Simucad Design Automation Inc.
Simucad Inc.
Simulation Technologies Corp
SimuQuest, Inc.
Simutech Corporation
SiVerion, Inc.
SkillCAD, Inc.
SmartDV Technologies
Smartech Oy
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[Home](https://semiengineering.com/%20/%20) \> [Knowledge Centers](https://semiengineering.com/%20/%20knowledge-center/) \> Error Correction Code (ECC)
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# Error Correction Code (ECC)
[Back to Knowledge Center](https://semiengineering.com/knowledge-center/)
### Tags
[ECC](https://semiengineering.com/tag/ECC/) [error correction code](https://semiengineering.com/tag/error-correction-code/) [error correcting code](https://semiengineering.com/tag/error-correcting-code/) [memory](https://semiengineering.com/tag/memory/) [DRAM](https://semiengineering.com/tag/DRAM/) [Hamming codes](https://semiengineering.com/tag/Hamming-codes/)
### Top Stories & Special Reports
- [Extra Safety Measures Needed For Aerospace ICs](https://semiengineering.com/extra-safety-measures-needed-for-aerospace-ics/)
Published on May 1, 2025
- [DRAM Test And Inspection Just Gets Tougher](https://semiengineering.com/dram-test-and-inspection-just-gets-tougher/)
Published on November 7, 2023
- [DRAM Thermal Issues Reach Crisis Point](https://semiengineering.com/dram-thermal-issues-reach-crisis-point/)
Published on June 9, 2022
- [More Errors, More Correction in Memories](https://semiengineering.com/more-errors-more-correction-in-memories/)
Published on November 9, 2021
- [Targeting Redundancy In ICs](https://semiengineering.com/redundancy-resiliency-and-robustness/)
Published on June 14, 2021
- [Taming Novel NVM Non-Determinism](https://semiengineering.com/taming-novel-nvm-non-determinism/)
Published on March 10, 2020
- [Logic Chip, Heal Thyself](https://semiengineering.com/logic-chip-heal-thyself/)
Published on February 11, 2020
### Research
- [Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)](https://semiengineering.com/pathfinding-method-that-models-ecc-overhead-for-chiplet-interconnects-ucla/)
Published on March 16, 2026
- [Loss Errors in Error-Corrected Circuits Across A Range Of Quantum Hardware Platforms (MIT, Harvard, QuEra)](https://semiengineering.com/loss-errors-in-error-corrected-circuits-across-a-range-of-quantum-hardware-platforms-mit-harvard-quera/)
Published on January 13, 2026
- [Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)](https://semiengineering.com/reliability-extension-architecture-for-cost-effective-hbm-rpi-scaleflux-ibm-tj-watson/)
Published on January 1, 2026
- [Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)](https://semiengineering.com/cost-effective-orthogonal-approach-to-resilient-memory-design-univ-of-central-florida-ut-san-antonio-rochester/)
Published on September 16, 2025
- [Low-Latency Interconnect for Close-Coupled On-Chip Communication With Error Correction Code Protection (ETH Zurich)](https://semiengineering.com/low-latency-interconnect-for-close-coupled-on-chip-communication-with-error-correction-code-protection-eth-zurich/)
Published on August 11, 2025
- [Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors](https://semiengineering.com/using-formal-verification-to-evaluate-the-hw-reliability-of-a-risc-v-ibex-core-in-the-presence-of-soft-errors/)
Published on May 31, 2024
- [HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes](https://semiengineering.com/harp-practically-and-effectively-identifying-uncorrectable-errors-in-memory-chips-that-use-on-die-error-correcting-codes/)
Published on November 18, 2021
- [Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers](https://semiengineering.com/buried-nanomagnet-realizing-high-speed-low-variability-silicon-spin-qubits-implementable-in-error-correctable-large-scale-quantum-computers/)
Published on October 27, 2021
### Blogs & White Papers
- [Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction](https://semiengineering.com/programmable-hardware-delivers-10000x-improvement-in-verification-speed-over-software-for-forward-error-correction-2/)
Published on August 28, 2025
- [Data Integrity For JEDEC DRAM Memories](https://semiengineering.com/data-integrity-for-jedec-dram-memories/)
Published on July 19, 2022
- [Accelerating 5G Baseband With Adaptive SoCs](https://semiengineering.com/accelerating-5g-baseband-with-adaptive-socs/)
Published on July 15, 2021
- [Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP](https://semiengineering.com/getting-ready-for-an-efficient-shift-to-pci-express-6-0-designs-with-optimized-ip/)
Published on June 10, 2021
- [What Designers Need to Know About Error Correction Code (ECC) In DDR Memories](https://semiengineering.com/what-designers-need-to-know-about-error-correction-code-ecc-in-ddr-memories/)
Published on December 10, 2020
- [When You Canât Afford To Scrimp On System Reliability](https://semiengineering.com/when-you-cant-afford-to-scrimp-on-system-reliability/)
Published on August 6, 2020
- [SerDes For Chiplets](https://semiengineering.com/serdes-for-chiplets/)
Published on October 16, 2018
- [A Dual-Mode Error-Correcting Code Solution For 50Gbps Ethernet](https://semiengineering.com/a-dual-mode-error-correcting-code-solution-for-50gbps-ethernet/)
Published on October 25, 2017
- [When DDR DRAM Is Right For Automotive Systems](https://semiengineering.com/when-ddr-dram-is-right-for-automotive-systems/)
Published on January 12, 2017
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### Enterprise-Class DRAM Reliability
March 6th, 2020
### Parent Centers
- [Memory](https://semiengineering.com/knowledge_centers/memory/)
- [DRAM: Dynamic Random Access Memory](https://semiengineering.com/knowledge_centers/memory/volatile-memory/dynamic-random-access-memory/)
# [2\.5D](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/2-5d-ic/)
Multiple chips arranged in a planar or stacked configuration with an interposer for communication.
# [2D Materials](https://semiengineering.com/knowledge_centers/materials/2d-materials/)
# [3D NAND](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/flash-memory/3d-nand/)
Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.
But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.
Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.
In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.
In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.
One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.
The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.
Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.
Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.
Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a âmacaroni channel,â according to Objective Analysis.
Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.
Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.
# [3D Transistors](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/)
Transistors where source and drain are added as fins of the gate.
# [3D-ICs](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/3d-ics/)
2\.5D and 3D forms of integration
# [5G](https://semiengineering.com/knowledge_centers/data-movement/wireless/5g/)
Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.
# [6G](https://semiengineering.com/knowledge_centers/data-movement/wireless/6g/)
# [A brief history of design](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design/a-brief-history-of-design/)
We start with schematics and end with ESL
# [A brief history of logic simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/a-brief-history-of-logic-simulation/)
Important events in the history of logic simulation
# [A brief history of logic synthesis](https://semiengineering.com/knowledge_centers/eda-design/definitions/a-brief-history-of-logic-synthesis/)
Early development associated with logic synthesis
# [Acronyms](https://semiengineering.com/knowledge_centers/acronyms/)
Commonly and not-so-commonly used acronyms.
The following is a list of acronyms and what they stand for:
ACK - Acknowledge
ADC - Analog to Digital Converter
AI - Artificial Intelligence
ALD - Atomic Layer Deposition
ALE - Atomic Layer Etch
AMOLED - Active-Matrix OLED
AMP - Asymmetric Multi Processing
AOI - Automated Optical Inspection
AP - Access Point
ASIC - Application Specific Integrated Circuit
ATE - Automatic Test Equipment
BEOL - Back-End-Of-Line
BGA - Ball Grid Array
BSA - Basic Service Area
BTI - Bias-Temperature Instability
CA - Collision Avoidance
CBRAM - Conductive Bridging RAM
CCI - Cache Coherent Interconnect
CD Collision Detection
CF - Contention-Free
CFP - Contention-Free Period
CP - Contention Period
CPU - Central Processing Unit
CRC - Cyclic Redundancy Check
CSMA - Carrier Sense, Multiple Access
CFD - Computational Fluid Dynamic
CMOS - Complementary Metal Oxide Semiconductor
CNN - Convolutional Neural Network
CPP - Contacted Poly Pitch
CSP - Chip Scale Packaging
CTS - Clear To Send
DAC - Digital to Analog Convertor
DARPA - Defense Advanced Research Projects Agency
DCF - Distributed Coordination Function
DDR - Double Data Rate
DFA - Differential Fault Analysis
DFT - Design for Test
DFM - Design for Manufacturing
DIFS - Distributed Inter-frame Space
DPA - Differential Power Analysis
DL - Deep Learning
DRAM - Dynamic Random Access Memory
DRC - Design Rule Checker
DSA - Directed Self Assembly
DSP - Digital Signal Processor
DUT - Design Under Test
DUV - Design Under Verification
DVFS - Dynamic Voltage and Frequency Scaling
ECO - Engineering Change Order
EDA - Electronic Design Automation
EM - Electromagnetic
EM - Electromigration
ESL - Electronic System Level
EUV - Extreme Ultraviolet
FD-SOI - Fully Depleted Silicon on Insulator
FEOL - Front-End-Of-Line
FET - Field Effect Transistor
FIFO - First In First Out
FPGA - Field Programmable Gate Array
GAA - Gate-All-Around
GaAs - Gallium Arsenide
GaN - Gallium Nitride
GPU - Graphics Processing Unit
HBM - High Bandwidth Memory
HBT - Heterojunction Bipolar Transistor
HDL - Hardware Description Language
HMC - Hybrid Memory Cube
IC - Integrated Circuit
IEEE - Institute of Electrical and Electronics Engineers
IIC - Industrial Internet Consortium
IIoT - Industrial Internet of Things
IoT - Internet of Things
IP - Intellectual Property
IR - Infra-red
ISM - Industrial, Scientific, Medical
ISS - Instruction Set Simulator
ILT - Inverse Lithography Technology
JTAG - Joint Test Action Group
LAN - Local Area Network
LCD - Liquid Crystal Display
LTE - Long-Term Evolution
MAC -Media Access Control
MCU - Microcontroller
MEMS - Micro Electrical Mechanical Systems
MES - Manufacturing Execution Systems
ML-Machine Learning
MOL - Middle-Of-Line
MRAM - Magnetic Random Access Memory
NA - Numerical Aperture
NGL - Next-Generation Lithography
NIC - Network Interface Card
NSF - National Science Foundation
NVM - Non-Volatile Memory
OCAP - Out of Control Action Plan
OLED - Organic Light-Emitting Diode
OPC - Optical Proximity Correction
OS - Operating System
OSAT - Outsourced Semiconductor Assembly and Test
OTP - One Time Programmable
PCB - Printed Circuit Board
PCF - Point Coordination Function
PCM - Phase-Change Memory
PDK - Process Design Kit
PDN - Power Delivery Network
PHY - Physical Layer
PI - Power Integrity
PIFS - Point Inter-frame Space
PnR - Place and Route
PoP - Package-on-Package
PPA - Power, Performance, Area
PPAC - Power, Performance, Area, Cost
PRNG - Pure Random Number Generator
PVT - Process, Voltage, Temperature
RAM - Random Access Memory
RC4 - Rivest Cipher 4
RDL - Register Definition Language
RDL - Redistribution Layer
RF - Radio Frequency
ROM - Read Only Memory
RoT - Root Of Trust
RTL - Register Transfer Level
RTOS - Real Time Operating System
RTS - Request To Send
SCM - Storage Class Memory
SerDes - Serializer / Deserializer
SIFS - Short Inter-frame Space
SI - Signal Integrity
SiC - Silicon Carbide
SiGe - Silicon Germanium
SK - Shared Key
SMP - Symmetric Multi Processing
SoC - System on Chip
SOI - Silicon on Insulator
SPA - Simple Power Analysis
SRAF - Sub-Resolution Assist Features
SRAM - Static Random Access Memory
SSD - Solid-state Storage Drives
SSID - Service Set Identifier
STA - Static Timing Analysis
STI - Shallow Trench Isolation
TLM - Transaction Level Model
TSV - Through Silicon Via
UPF - Unified Power Format
USB - Universal Serial Bus
UVM - Universal Verification Methodology
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
VSLI - Very Large Scale Integration
VIP - Verification Intellectual Property
VoWi-Fi - Voice over Wi-Fi
Vt - theshold Voltage
Wan - Wide Area Network
WEP - Wired Equivalency Protocol
Wi-Fi - Wireless High Fidelity
WiGIG - Gigabit Wi-Fi
WLAN - Wireless Local Area Network
WLP - Wafer Level Packaging
WPA - Wi-Fi Protected Access
# [ADAS: Advanced Driver Assistance Systems](https://semiengineering.com/knowledge_centers/automotive/adas-advanced-driver-assistance-systems/)
Sensing and processing to make driving safer.
# [Advanced Packaging](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/)
Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.
While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.
These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.
# [Advanced Packaging Fundamentals eBook (2025-2026)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/ebook-advanced-packaging-fundamentals/)
# [Agile](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/agile/)
An approach to software development focusing on continual delivery and flexibility to changing requirements
# [Agile Hardware Development](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/agile/agile-hardware-development/)
How Agile applies to the development of hardware systems
# [Air Gap](https://semiengineering.com/knowledge_centers/manufacturing/process/air-gap/)
A way of improving the insulation between various components in a semiconductor by creating empty space.
# [Amdahlâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/amdahls-law/)
The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.
# [Analog](https://semiengineering.com/knowledge_centers/eda-design/definitions/analog/)
Semiconductors that measure real-world conditions
# [Analog circuits](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/analog-circuits/)
Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.
# [Analog Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/definitions/analog/analog-design-and-verification/)
The design and verification of analog components.
# [Application Programming Interface (API)](https://semiengineering.com/knowledge_centers/user-interfaces/application-programming-interface-api/)
A software tool used in software programming that abstracts all the programming steps into a user interface for the developer.
# [Application Specific Integrated Circuit (ASIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/application-specific-integrated-circuit-asic/)
A custom, purpose-built integrated circuit made for a specific task or product.
# [Application-Specific Standard Product (ASSP)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/assp-application-specific-standard-product/)
An IC created and optimized for a market and sold to multiple companies.
# [Architectures](https://semiengineering.com/knowledge_centers/compute-architectures/)
# [Artificial Intelligence (AI)](https://semiengineering.com/knowledge_centers/artificial-intelligence/)
Using machines to make decisions based upon stored knowledge and sensory input.
# [Assertion](https://semiengineering.com/knowledge_centers/eda-design/verification/formal-verification/assertion/)
Code that looks for violations of a property
# [Atomic Force Microscopy (AFM), Atomic Force Microscope (AFM)](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/atomic-force-microscopy-afm-atomic-force-microscope-afm/)
A method of measuring the surface structures down to the angstrom level.
# [Atomic Layer Deposition (ALD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/atomic-layer-deposition/)
A method of depositing materials and films in exact places on a surface.
# [Atomic Layer Etch (ALE)](https://semiengineering.com/knowledge_centers/manufacturing/process/atomic-layer-etch/)
ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.
# [Automatic Test Equipment (ATE)](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/automatic-test-equipment-ate/)
# [Automatic Test Pattern Generation (ATPG)](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/)
The generation of tests that can be used for functional or manufacturing verification
# [Automotive](https://semiengineering.com/knowledge_centers/automotive/)
Issues dealing with the development of automotive electronics.
# [Automotive Ethernet, Time Sensitive Networking (TSN)](https://semiengineering.com/knowledge_centers/automotive/automotive-ethernet-time-sensitive-networking-tsn/)
Time sensitive networking puts real time into automotive Ethernet.
# [Automotive Standards](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/)
# [Autonomous Vehicles](https://semiengineering.com/knowledge_centers/automotive/autonomous-vehicles/)
# [Avalanche Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/avalanche-noise/)
Noise in reverse biased junctions
# [AVM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/avm/)
Verification methodology created by Mentor
# [Backend-of-the-line (BEOL)](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/)
IC manufacturing processes where interconnects are made.
# [Backside Power Delivery Network (BPDN)](https://semiengineering.com/knowledge_centers/low-power/backside-power-delivery-network/)
# [Bandgap, Band Gap](https://semiengineering.com/knowledge_centers/materials/band-gap/)
# [Batteries](https://semiengineering.com/knowledge_centers/low-power/batteries/)
Devices that chemically store energy.
# [Behavioral Synthesis](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/behavioral-synthesis/)
Transformation of a design described in a high-level of abstraction to RTL
# [Blech Effect](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/blech-effect/)
A reverse force to electromigration.
# [Bluetooth, Bluetooth Low Energy (BLE)](https://semiengineering.com/knowledge_centers/data-movement/wireless/bluetooth-low-energy-2/)
Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.
# [Brazil](https://semiengineering.com/knowledge_centers/regional-developments-issues/brazil/)
# [BSIM](https://semiengineering.com/knowledge_centers/eda-design/models/bsim/)
Transistor model
# [Built-in self-test (BiST)](https://semiengineering.com/knowledge_centers/test/built-in-self-test-bist/)
On-chip logic to test a design.
# [Bunch of Wires (BoW)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/bunch-of-wires-bow/)
Chiplet interconnect specification.
# [Bus Functional Model](https://semiengineering.com/knowledge_centers/eda-design/models/bus-functional-model/)
Interface model between testbench and device under test
# [C, C++](https://semiengineering.com/knowledge_centers/languages/c-c/)
C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.
# [Cache Coherent Interconnect for Accelerators (CCIX)](https://semiengineering.com/knowledge_centers/standards-laws/standards/cache-coherent-interconnect-for-accelerators-ccix/)
Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.
# [CD-SEM: Critical-Dimension Scanning Electron Microscope](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/cd-sem/)
CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.
# [CDC design principles](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/cdc-design-principles/)
Making CDC interfaces predictable
# [Cell-Aware Test](https://semiengineering.com/knowledge_centers/test/cell-aware-test/)
Fault model for faults within cells
# [Cell-Aware Test for FinFET](https://semiengineering.com/knowledge_centers/test/cell-aware-test/cell-aware-test-for-finfet/)
Cell-aware test methodology for addressing defect mechanisms specific to FinFETs.
# [Central Processing Unit (CPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/central-processing-unit-cpu/)
The CPU is an dedicated integrated circuit or IP core that processes logic and math.
# [Characterization/Metrology Lab](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/characterization-metrology-lab/)
A lab that wrks with R\&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.
# [Checker](https://semiengineering.com/knowledge_centers/eda-design/verification/checker/)
Testbench component that verifies results
# [Chemical Vapor Deposition (CVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/chemical-vapor-deposition/)
A process used to develop thin films and polymer coatings.
# [China](https://semiengineering.com/knowledge_centers/regional-developments-issues/china/)
# [Chip Design](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design/)
Design is the process of producing an implementation from a conceptual form
# [Chip Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design-and-verification/)
The design, verification, implementation and test of electronics systems into integrated circuits.
# [Chip Thermal Interface Protocol](https://semiengineering.com/knowledge_centers/low-power/techniques/chip-thermal-interface-protocol/)
Exchange of thermal design information for 3D ICs
# [Chiplet Fundamentals For Engineers: 2026 eBook](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/chiplets/chiplets-deep-dive-into-designing-manufacturing-and-testing/)
# [Chiplets](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/chiplets/)
A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.
There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.
With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.
A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.
Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandouâs chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandouâs interconnect technology.
DARPAâs approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.
The CHIPS program started in 2017. The program has various types of contractors/sub-contractorsâmanufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).
# [Clock Domain Crossing (CDC)](https://semiengineering.com/knowledge_centers/eda-design/verification/clock-domain-crossing/)
Asynchronous communications across boundaries
# [Clock Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/clock-gating-2/)
Dynamic power reduction by gating the clock
# [Clock Tree Optimization](https://semiengineering.com/knowledge_centers/low-power/techniques/clock-tree-optimization/)
Design of clock trees for power reduction
# [CMOS](https://semiengineering.com/knowledge_centers/materials/cmos/)
Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.
CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.
# [Co-Packaged Optics](https://semiengineering.com/knowledge_centers/data-movement/photonics/co-packaged-optics/)
# [Code Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/code-coverage/)
Metrics related to about of code executed in functional verification
# [Combinatorial Equivalence Checking](https://semiengineering.com/knowledge_centers/eda-design/definitions/combinatorial-equivalence-checking/)
Verify functionality between registers remains unchanged after a transformation
# [Companies & Organizations](https://semiengineering.com/knowledge_centers/entities/)
# [Compiled-code Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/compiled-code-simulation/)
Faster form for logic simulation
# [Complementary FET (CFET)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/cfet/)
Complementary FET, a new type of vertical transistor.
# [Compound Semiconductors](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/)
Combinations of semiconductor materials.
# [Compute Express Link (CXL)](https://semiengineering.com/knowledge_centers/standards-laws/standards/compute-express-link-cxl/)
Interconnect between CPU and accelerators.
# [Contact](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/contact/)
The structure that connects a transistor with the first layer of copper interconnects.
# [Convolutional Neural Network (CNN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/convolutional-neural-network/)
A technique for computer vision based on machine learning.
# [Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/)
Completion metrics for functional verification
# [Crosstalk](https://semiengineering.com/knowledge_centers/eda-design/noise-2/crosstalk/)
Interference between signals
# [Crypto processors](https://semiengineering.com/knowledge_centers/semiconductor-security/crypto-processors/)
Crypto processors are specialized processors that execute cryptographic algorithms within hardware.
# [Dark Silicon](https://semiengineering.com/knowledge_centers/low-power/techniques/dark-silicon/)
A method of conserving power in ICs by powering down segments of a chip when they are not in use.
# [Data Analytics](https://semiengineering.com/knowledge_centers/test/data-analytics/)
Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.
# [Data Analytics & Test](https://semiengineering.com/knowledge_centers/test/)
How semiconductors are sorted and tested before and after implementation of the chip in a system.
# [Data Movement](https://semiengineering.com/knowledge_centers/data-movement/)
The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.
# [Debug](https://semiengineering.com/knowledge_centers/eda-design/verification/debug/)
The removal of bugs from a design
# [Deep Learning (DL)](https://semiengineering.com/knowledge_centers/artificial-intelligence/machine-learning/deep-learning/)
Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.
# [Definitions](https://semiengineering.com/knowledge_centers/eda-design/definitions/)
# [Dennardâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/dennards-law/)
An observation that as features shrink, so does power consumption.
# [Deposition](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/)
# [Design for Manufacturing (DFM)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/design-for-manufacturing-dfm/)
Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.
# [Design for Test (DFT)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/design-for-test-dft/)
Techniques that reduce the difficulty and cost associated with testing an integrated circuit.
# [Design Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/design-patent/)
Protection for the ornamental design of an item
# [Design Rule Checking (DRC)](https://semiengineering.com/knowledge_centers/eda-design/verification/design-rule-checking-drc/)
A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer
# [Design Rule Pattern Matching](https://semiengineering.com/knowledge_centers/eda-design/verification/design-rule-pattern-matching/)
Locating design rules using pattern matching techniques.
# [Device Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/device-noise/)
Sources of noise in devices
# [DFT and Clock Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/dft-and-clock-gating/)
Insertion of test logic for clock-gating
# [Diamond Semiconductors](https://semiengineering.com/knowledge_centers/materials/diamond-semiconductors/)
A wide-bandgap synthetic material.
# [Digital IP](https://semiengineering.com/knowledge_centers/intellectual-property/digital-ip/)
Categorization of digital IP
# [Digital Oscilloscope](https://semiengineering.com/knowledge_centers/test/digital-oscilloscope/)
Allowed an image to be saved digitally
# [Digital Signal Processor (DSP)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/digital-signal-processor-dsp/)
A digital signal processor is a processor optimized to process signals.
# [Digital Twins](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/digital-twins/)
A digital representation of a product or system.
# [Directed Self-Assembly (DSA)](https://semiengineering.com/knowledge_centers/manufacturing/process/directed-self-assembly/)
A complementary lithography technology.
# [DNA biometrics](https://semiengineering.com/knowledge_centers/semiconductor-security/biometrics/dna-biometrics/)
DNA analysis is based upon unique DNA sequencing.
# [Domain/Distributed Architecture](https://semiengineering.com/knowledge_centers/automotive/domain-distributed-architecture/)
# [Double Data Rate (DDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/dynamic-random-access-memory/double-data-rate-ddr/)
# [Double Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/)
A patterning technique using multiple passes of a laser.
# [Double Patterning Methodologies](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/double-patterning-methodologies/)
Colored and colorless flows for double patterning
# [DRAM: Dynamic Random Access Memory](https://semiengineering.com/knowledge_centers/memory/volatile-memory/dynamic-random-access-memory/)
Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.
Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.
In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.
DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.
Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.
The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.
Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these
The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.
# [Dynamic Voltage and Frequency Scaling (DVFS)](https://semiengineering.com/knowledge_centers/low-power/techniques/dynamic-voltage-and-frequency-scaling/)
Dynamically adjusting voltage and frequency for power reduction
# [e](https://semiengineering.com/knowledge_centers/languages/e/)
Hardware Verification Language
# [E-beam Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/e-beam-inspection/)
A slower method for finding smaller defects.
# [E-Beam Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/ebeam/)
Lithography using a single beam e-beam tool
# [EBooks by Semiconductor Engineering](https://semiengineering.com/knowledge_centers/ebooks-by-semiconductor-engineering/)
# [EDA & Design](https://semiengineering.com/knowledge_centers/eda-design/)
# [Edge AI](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/)
# [Edge Computing](https://semiengineering.com/knowledge_centers/edge-computing/)
# [Edge Placement Error (EPE)](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/edge-placement-error/)
The difference between the intended and the printed features of an IC layout.
# [Electromigration](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/electromigration/)
Electromigration (EM) due to power densities
# [Electronic Design Automation (EDA)](https://semiengineering.com/knowledge_centers/eda-design/definitions/electronic-design-automation/)
Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.
# [Electronic System Level (ESL)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/electronic-system-level/)
Levels of abstraction higher than RTL used for design and verification
# [Electrostatic Discharge (ESD)](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/electrostatic-discharge-esd/)
Transfer of electrostatic charge.
# [Embedded FPGA (eFPGA)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/fpga/embedded-fpga-efpga/)
An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.
# [Emulation](https://semiengineering.com/knowledge_centers/eda-design/verification/emulation/)
Special purpose hardware used for logic verification
# [Energy Harvesting](https://semiengineering.com/knowledge_centers/low-power/techniques/energy-harvesting/)
Capturing energy from the environment
# [Engineers: Jobs & Education](https://semiengineering.com/knowledge_centers/engineering-jobs-education/)
# [Environmental Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/environmental-noise/)
Noise caused by the environment
# [Epitaxy](https://semiengineering.com/knowledge_centers/manufacturing/process/epitaxy/)
A method for growing or depositing mono crystalline films on a substrate.
# [eRM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/erm/)
Reuse methodology based on the e language
# [**Error Correction Code (ECC)** (where you are)](https://semiengineering.com/knowledge_centers/memory/error-correction-code-ecc/)
Methods for detecting and correcting errors.
# [Ethernet](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/ethernet/)
Ethernet is a reliable, open standard for connecting devices by wire.
# [EUV: Extreme Ultraviolet Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/euv/)
EUV lithography is a soft X-ray technology.
# [Failure Analysis](https://semiengineering.com/knowledge_centers/manufacturing/process/failure-analysis/)
Finding out what went wrong in semiconductor design and manufacturing.
# [Fan-Outs](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/fan-outs/)
A way of including more features that normally would be on a printed circuit board inside a package.
# [Fault Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/fault-simulation/)
Evaluation of a design under the presence of manufacturing defects
# [Ferroelectric FETs (FeFET)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/fefets/)
Ferroelectric FET is a new type of memory.
# [Field Programmable Gate Array (FPGA)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/fpga/)
Reprogrammable logic device
# [FinFET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/finfet-3/)
A three-dimensional transistor.
# [Flash Memory](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/flash-memory/)
Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.
The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.
Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.
With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.
# [Flexible Hybrid Electronics (FHE)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/flexible-hybrid-electronics-fhe/)
Integrated circuits on a flexible substrate
# [FlexRay ISO 17458](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/flexray/)
An automotive communications protocol
# [Flicker Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/flicker-noise/)
Noise related to resistance fluctuation
# [Flip-Chip](https://semiengineering.com/knowledge_centers/packaging/flip-chip/)
A type of interconnect using solder balls or microbumps.
# [Forksheet FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/forksheet-fet/)
A transistor type with integrated nFET and pFET.
# [Formal Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/formal-verification/)
Formal verification involves a mathematical proof to show that a design adheres to a property
# [Foundry, pure-play foundry](https://semiengineering.com/knowledge_centers/manufacturing/foundry-pure-play-foundry/)
A company that specializes in manufacturing semiconductor devices.
# [Functional Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/functional-coverage/)
Coverage metric used to indicate progress in verifying functionality
# [Functional Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/functional-design-and-verification/)
Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.
# [Functional Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/functional-verification/)
Functional verification is used to determine if a design, or unit of a design, conforms to its specification.
# [Gage R\&R, Gage Repeatability And Reproducibility](https://semiengineering.com/knowledge_centers/test/gage-rr-gage-repeatability-and-reproducibility/)
A statistical method for determining if a test system is production ready by measuring variation during test for repeatability and reproducibility.
# [Gallium Nitride (GaN)](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/gallium-nitride/)
GaN is a III-V material with a wide bandgap.
# [Gate-All-Around FET (GAA FET)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/gate-all-around-fet/)
A transistor design with a gate is placed on all four sides of the channel.
# [Gate-Level Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/gate-level-power-optimizations/)
Power reduction techniques available at the gate level.
# [Generation-Recombination Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/generation-recombination-noise/)
noise related to generation-recombination
# [Generative Adversarial Network (GAN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/generative-adversarial-network-gan/)
A neural network framework that can generate new data.
# [Germany](https://semiengineering.com/knowledge_centers/regional-developments-issues/germany/)
Germany is known for its automotive industry and industrial machinery.
# [Graphene](https://semiengineering.com/knowledge_centers/materials/2d-materials/graphene/)
Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.
The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.
Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2â
Vâ1â
sâ1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.
While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.
# [Graphics Double Data Rate (GDDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/graphics-double-data-rate-gddr/)
# [Graphics Processing Unit (GPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/graphics-processing-unit-gpu/)
An electronic circuit designed to handle graphics and video.
# [Guard Banding](https://semiengineering.com/knowledge_centers/eda-design/definitions/guard-banding/)
Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.
# [Hard IP](https://semiengineering.com/knowledge_centers/intellectual-property/hard-ip/)
Fully designed hardware IP block
# [Hardware Assisted Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/hardware-assisted-verification/)
Use of special purpose hardware to accelerate verification
# [Hardware Modeler](https://semiengineering.com/knowledge_centers/eda-design/models/hardware-modeler/)
Historical solution that used real chips in the simulation process
# [hardware/software co-design](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hardware-software-co-design/)
Optimizing the design by using a single language to describe hardware and software.
# [Heat Dissipation](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/heat-dissipation/)
Power creates heat and heat affects power
# [Heterogeneous Integration](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/heterogeneous-integration/)
The process of integrating different chips, chiplets, and chip components into packages.
# [High-Bandwidth Memory (HBM)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/high-bandwidth-memory/)
A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.
# [High-Density Advanced Packaging (HDAP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/high-density-advanced-packaging-hdap/)
An umbrella term (circa 2015) for advanced packaging in semiconductors.
# [High-Level Synthesis (HLS)](https://semiengineering.com/knowledge_centers/eda-design/verification/high-level-synthesis/)
Synthesis technology that transforms an untimed behavioral description into RTL
# [HSA Platform System Architecture Specification](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hsa-platform-system-architecture-specification/)
Defines a set of functionality and features for HSA hardware
# [HSA Runtime Programmerâs Reference Manual](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hsa-runtime-programmeraes-reference-manual/)
Runtime capabilities for the HSA architecture
# [Hybrid Bonding](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/hybrid-bonding/)
# [IC Types](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/)
What are the types of integrated circuits?
# [IEEE 1076-VHSIC HW Description Language](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076/)
Hardware Description Language
# [IEEE 1076.1-Analog & Mixed-Signal](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-1/)
Analog extensions to VHDL
# [IEEE 1076.1.1-VHDL-AMS Standard Packages](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-1-1/)
A collection of VHDL 1076.1 packages
# [IEEE 1076.4-VHDL Synthesis Package â Floating Point](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-4/)
Modeling of macro-cells in VHDL
# [IEEE 1149 Boundary Scan Test](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1149/)
Boundry Scan Test
# [IEEE 1364-Verilog](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1364/)
IEEE ratified version of Verilog
# [IEEE 1364.1-Verilog RTL Synthesis](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1364-1/)
Standard for Verilog Register Transfer Level Synthesis
# [IEEE 1532- in-system programmability (ISP)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1532/)
Extension to 1149.1 for complex device programming
# [IEEE 1647-Functional Verification Language e](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1647/)
Functional verification language
# [IEEE 1666-Standard SystemC](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1666/)
SystemC
# [IEEE 1685-IP-XACT](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1685/)
Standard for integration of IP in System-on-Chip
# [IEEE 1687-IEEE Standard for Access and Control of Instrumentation Embedded](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1687/)
IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
# [IEEE 1800-SystemVerilog](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1800/)
IEEE ratified version of SystemVerilog
# [IEEE 1800.2âUVM](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1800-2/)
Universal Verification Methodology
# [IEEE 1801-Design/Verification of Low-Power, Energy-Aware UPF](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1801/)
IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)
# [IEEE 1838: Test Access Architecture for 3D Stacked IC](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1838/)
Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
# [IEEE 1850-Property Specification Language (PSL)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1850/)
Verification language based on formal specification of behavior
# [IEEE 802.1-Higher Layer LAN Protocols](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-1-higher-layer-lan-protocols/)
IEEE 802.1 is the standard and working group for higher layer LAN protocols.
# [IEEE 802.11-Wireless LAN](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-11-wireless-lan/)
IEEE 802.11 working group manages the standards for wireless local area networks (LANs).
# [IEEE 802.15-Wireless Specialty Networks (WSN)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-15-wireless-specialty-networks-wsn/)
IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.
# [IEEE 802.18-Radio Regulatory TAG](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-18-radio-regulatory/)
"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.
# [IEEE 802.19-Wireless Coexistence](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-19-wireless-coexistence/)
Standards for coexistence between wireless standards of unlicensed devices.
# [IEEE 802.3-Ethernet](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-3-ethernet/)
IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.
# [IEEE P2415: Unified HW Abstraction & Layer for Energy Proportional Electronic Systems](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-p2415/)
Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
# [IEEE P2416-Power Modeling](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-p2416/)
Power Modeling Standard for Enabling System Level Analysis
# [IEEE-ISTO 5001 (Nexus 5001) â embedded processor debug](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-isto-5001-standard-nexus-5001/)
# [IIoT: Industrial Internet of Things](https://semiengineering.com/knowledge_centers/edge-computing/industrial-internet-of-things/)
Specific requirements and special consideration for the Internet of Things within an Industrial setting.
# [Impact of lithography on wafer costs](https://semiengineering.com/knowledge_centers/manufacturing/lithography/impact-of-lithography-on-wafer-costs/)
Wafer costs across nodes
# [Implementation Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/implementation-power-optimizations/)
Power optimization techniques for physical implementation
# [In-Memory Computing](https://semiengineering.com/knowledge_centers/compute-architectures/in-memory-computing/)
Performing functions directly in the fabric of memory.
# [Induced Gate Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/induced-gate-noise/)
Thermal noise within a channel
# [Insulated-Gate Bipolar Transistors (IGBT)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/insulated-gate-bipolar-transistors/)
IGBTs are combinations of MOSFETs and bipolar transistors.
# [Integrated Circuits (ICs)](https://semiengineering.com/knowledge_centers/integrated-circuit/)
Integration of multiple devices onto a single piece of semiconductor
# [Integrated Device Manufacturer (IDM)](https://semiengineering.com/knowledge_centers/manufacturing/integrated-device-manufacturer-idm/)
A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).
# [Intellectual Property (IP)](https://semiengineering.com/knowledge_centers/intellectual-property/)
A design or verification unit that is pre-packed and available for licensing.
# [Inter Partes Review](https://semiengineering.com/knowledge_centers/standards-laws/patents/inter-partes-review/)
Method to ascertain the validity of one or more claims of a patent
# [Interconnects](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/)
# [Interconnects (BEOL)](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/interconnect/)
Buses, NoCs and other forms of connection between various elements in an integrated circuit.
# [Internet of Things (IoT)](https://semiengineering.com/knowledge_centers/edge-computing/internet-of-things/)
Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.
# [Interposers](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/2-5d-ic/interposers/)
Fast, low-power inter-die conduits for 2.5D electrical signals.
# [Inverse Lithography Technology (ILT)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/inverse-lithography-technology-ilt/)
Finding ideal shapes to use on a photomask.
# [Ion Implants](https://semiengineering.com/knowledge_centers/manufacturing/process/ion-implants/)
Injection of critical dopants during the semiconductor manufacturing process.
# [IP-XACT](https://semiengineering.com/knowledge_centers/standards-laws/standards/ip-xact/)
Standard for integration of IP in System-on-Chip
# [IR Drop](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/ir-drop/)
The voltage drop when current flows through a resistor.
# [ISO 21434 / SAE 21434 Standard â Automotive cybersecurity](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-21434-sae-21434-standard-automotive-cybersecurity/)
# [ISO 26262 â Functional safety](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-26262/)
Standard related to the safety of electrical and electronic systems within a car
# [ISO/PAS 21448 â SOTIF](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-pas-21448-sotif/)
Standard to ensure proper operation of automotive situational awareness systems.
# [ISO/SAE FDIS 21434-Road Vehicles â Cybersecurity Engineering](https://semiengineering.com/knowledge_centers/standards-laws/standards/iso-sae-fdis-21434-road-vehicles-cybersecurity-engineering/)
A standard (under development) for automotive cybersecurity.
# [Israel](https://semiengineering.com/knowledge_centers/regional-developments-issues/israel/)
# [Issues](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/)
# [Koomeyâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/koomeys-law/)
The energy efficiency of computers doubles roughly every 18 months.
# [Languages](https://semiengineering.com/knowledge_centers/languages/)
Languages are used to create models
# [Large Language Models (LLMs)](https://semiengineering.com/knowledge_centers/artificial-intelligence/large-language-models/)
# [Laws](https://semiengineering.com/knowledge_centers/standards-laws/laws/)
Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.
# [Layout versus Schematic Checking (LVS)](https://semiengineering.com/knowledge_centers/eda-design/definitions/layout-versus-schematic-checking/)
Device and connectivity comparisons between the layout and the schematic
# [Level Shifters](https://semiengineering.com/knowledge_centers/low-power/techniques/level-shifters-2/)
Cells used to match voltages across voltage islands
# [Line Edge Roughness (LER)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/line-edge-roughness-ler/)
Deviation of a feature edge from ideal shape.
# [Lint](https://semiengineering.com/knowledge_centers/eda-design/verification/lint/)
Removal of non-portable or suspicious code
# [Litho Etch Litho Etch (LELE)](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/litho-etch-litho-etch/)
LELE is a form of double patterning
# [Litho Freeze Litho Etch](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/litho-freeze-litho-etch/)
A type of double patterning.
# [Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/)
Light used to transfer a pattern from a photomask onto a substrate.
# [Lithography k1 coefficient](https://semiengineering.com/knowledge_centers/manufacturing/lithography/lithography-k1-coefficient/)
Coefficient related to the difficulty of the lithography process
# [Logic Resizing](https://semiengineering.com/knowledge_centers/eda-design/definitions/logic-resizing-2/)
Correctly sizing logic elements
# [Logic Restructuring](https://semiengineering.com/knowledge_centers/eda-design/definitions/logic-restructuring-2/)
Restructuring of logic for power reduction
# [Logic Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/)
A simulator is a software process used to execute a model of hardware
# [Low Power Double Data Rate (LPDDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/low-power-double-data-rate-lpddr/)
# [Low Power Methodologies](https://semiengineering.com/knowledge_centers/low-power/techniques/low-power-methodologies/)
Methodologies used to reduce power consumption.
# [Low Power Verification](https://semiengineering.com/knowledge_centers/low-power/low-power-verification/)
Verification of power circuitry
# [Low-Power Design](https://semiengineering.com/knowledge_centers/low-power/low-power-design/)
# [Machine Learning (ML)](https://semiengineering.com/knowledge_centers/artificial-intelligence/machine-learning/)
An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.
# [Magnetoresistive RAM (MRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/)
Uses magnetic properties to store data
# [Makimotoâs Wave](https://semiengineering.com/knowledge_centers/standards-laws/laws/makimotos-wave/)
Observation related to the amount of custom and standard content in electronics.
# [Manufacturing Execution System (MES)](https://semiengineering.com/knowledge_centers/manufacturing/manufacturing-execution-system-mes/)
Tracking a wafer through the fab.
# [Manufacturing Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/manufacturing-noise/)
Noise sources in manufacturing
# [Materials](https://semiengineering.com/knowledge_centers/materials/)
Semiconductor materials enable electronic circuits to be constructed.
# [Memory](https://semiengineering.com/knowledge_centers/memory/)
A semiconductor device capable of retaining state information for a defined period of time.
# [MEMS](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/analog-circuits/mems/)
Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.
# [Metal Organic Chemical Vapor Deposition (MOCVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/metal-organic-chemical-vapor-deposition/)
A key tool for LED production.
# [Metastability](https://semiengineering.com/knowledge_centers/eda-design/definitions/metastability/)
Unstable state within a latch
# [Metcalfeâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/metcalfeaes-law/)
Observation that relates network value being proportional to the square of users
# [Methodologies and Flows](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/)
Describes the process to create a product
# [Metrology](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/)
Metrology is the science of measuring and characterizing tiny structures and materials.
# [Microcontroller (MCU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/microcontroller-mcu/)
A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.
# [Microprocessor, Microprocessor Unit (MPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/microprocessor-microprocessor-unit-mpu/)
The integrated circuit that first put a central processing unit on one chip of silicon.
# [Mixed-Signal](https://semiengineering.com/knowledge_centers/eda-design/definitions/mixed-signal/)
The integration of analog and digital.
# [Models](https://semiengineering.com/knowledge_centers/eda-design/models/)
# [Models and Abstractions](https://semiengineering.com/knowledge_centers/eda-design/models/models-and-abstractions/)
Models are abstractions of devices
# [Molded Interconnect Substrate (MIS)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/molded-interconnect-substrate/)
A midrange packaging option that offers lower density than fan-outs.
# [Monolithic 3D Chips](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/3d-ics/monolithic-3d-chips/)
A way of stacking transistors inside a single chip instead of a package.
# [Mooreâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/moores-law/)
Observation related to the growth of semiconductors by Gordon Moore.
# [Multi-Beam e-Beam Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/ebeam/multi-beam-ebeam-lithography/)
An advanced form of e-beam lithography
# [Multi-chip Modules (MCM)](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/multi-chip-modules/)
An early approach to bundling multiple functions into a single package.
# [Multi-Corner Multi-Mode (MCMM) Analysis](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/multi-corner-multi-mode-analysis/)
Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
# [Multi-Die Assemblies](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/)
# [Multi-site testing](https://semiengineering.com/knowledge_centers/test/multi-site-testing/)
Using a tester to test multiple dies at the same time.
# [Multi-Vt](https://semiengineering.com/knowledge_centers/low-power/techniques/multi-vt/)
Use of multi-threshold voltage devices
# [Multiple Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/multipatterning/)
A way to image IC designs at 20nm and below.
# [Nanoimprint Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/nanoimprint-lithography/)
A hot embossing process type of lithography.
# [Nanosheet FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/nanosheet-fet/)
A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.
# [Near Threshold Computing](https://semiengineering.com/knowledge_centers/low-power/techniques/near-threshold-computing/)
Optimizing power by computing below the minimum operating voltage.
# [Near-Memory Computing](https://semiengineering.com/knowledge_centers/compute-architectures/near-memory-computing/)
Moving compute closer to memory to reduce access costs.
# [Negative Bias Temperature Instability (NBTI)](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/negative-bias-temperature-instability/)
NBTI is a shift in threshold voltage with applied stress.
# [Network on Chip (NoC)](https://semiengineering.com/knowledge_centers/data-movement/network-on-chip-noc/)
An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.
# [Neural Networks](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/)
A method of collecting data from the physical world that mimics the human brain.
# [Neuromorphic Computing](https://semiengineering.com/knowledge_centers/compute-architectures/neuromorphic-computing/)
A compute architecture modeled on the human brain.
# [Nodes](https://semiengineering.com/knowledge_centers/manufacturing/process/nodes/)
Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.
# [Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/)
Random fluctuations in voltage or current on a signal.
# [Non-Volatile Memory (NVM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/)
Memory in which information is retained even when a power source is not present.
Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1
NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and whatâs being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.
Fundamentally, there are two types of NVM:
Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.
Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.
Then thereâs the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, itâs difficult to do it because the oxide thickness is not there to do to make it happen.
However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.
The OTP technology doesnât require the thicker oxide that is required for the MTP, and there is no floating gate.
1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/
# [Open Verification Methodology (OVM)](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/ovm/)
Verification methodology created from URM and AVM
# [Operand Isolation](https://semiengineering.com/knowledge_centers/low-power/techniques/operand-isolation-2/)
Disabling datapath computation when not enabled
# [Optical Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/optical-inspection/)
Method used to find defects on a wafer.
# [Optical Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/optical-lithography/)
# [Optical Proximity Correction (OPC)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/optical-proximity-correction-opc/)
A way to improve wafer printability by modifying mask patterns.
# [Original Equipment Manufacturer (OEM)](https://semiengineering.com/knowledge_centers/manufacturing/original-equipment-manufacturer-oem/)
The company that buys raw goods, including electronics and chips, to make a product.
# [Outsourced Semiconductor Assembly and Test (OSAT)](https://semiengineering.com/knowledge_centers/packaging/outsourced-semiconductor-assembly-and-test/)
Companies who perform IC packaging and testing - often referred to as OSAT
# [Overlay](https://semiengineering.com/knowledge_centers/manufacturing/lithography/overlay/)
The ability of a lithography scanner to align and print various layers accurately on top of each other.
# [package-on-package (PoP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/package-on-package-pop/)
# [Packaging](https://semiengineering.com/knowledge_centers/packaging/)
How semiconductors get assembled and packaged.
# [Part Average Testing (PAT)](https://semiengineering.com/knowledge_centers/test/part-average-testing-pat/)
Outlier detection for a single measurement, a requirement for automotive electronics.
# [Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/)
# [PCI Express (PCIe), Peripheral Component Interconnect Express](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/pci-express-pcie-peripheral-component-interconnect-express/)
High-speed serial expansion bus for connecting sending data between devices.
# [Pellicle](https://semiengineering.com/knowledge_centers/manufacturing/lithography/pellicle/)
A thin membrane that prevents a photomask from being contaminated.
# [Phase-Change Memory](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/phase-change-memory/)
Memory that stores information in the amorphous and crystalline phases.
# [Photomask](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/)
A template of what will be printed on a wafer.
# [Photonic Integrated Circuit (PIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/photonic-integrated-circuit-pic/)
# [Photonics](https://semiengineering.com/knowledge_centers/data-movement/photonics/)
# [Photoresist](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photoresist/)
Light-sensitive material used to form a pattern on the substrate.
# [Physical AI](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/physical-ai/)
# [Physical Design](https://semiengineering.com/knowledge_centers/eda-design/definitions/physical-design/)
Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.
# [Physical Layer (PHY)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/phy/)
Physically connects devices and is the conduit that encodes, decodes bits of data.
# [Physical Vapor Deposition (PVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/physical-vapor-deposition/)
PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.
# [Physical Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/physical-verification/)
Making sure a design layout works as intended.
# [Physically Unclonable Functions (PUFs)](https://semiengineering.com/knowledge_centers/semiconductor-security/physically-unclonable-functions/)
A set of unique features that can be built into a chip but not cloned.
# [Pin Swapping](https://semiengineering.com/knowledge_centers/low-power/techniques/pin-swapping-2/)
Lowering capacitive loads on logic
# [Planar](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/)
# [PODEM](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/podem/)
An algorithm used ATPG
# [Portable Stimulus (PSS)](https://semiengineering.com/knowledge_centers/languages/portable_stimulus/)
Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.
# [Power](https://semiengineering.com/knowledge_centers/low-power/)
# [Power Consumption](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-consumption/)
Components of power consumption
# [Power Cycle Sequencing](https://semiengineering.com/knowledge_centers/low-power/techniques/power-cycle-sequencing/)
Power domain shutdown and startup
# [Power Definitions](https://semiengineering.com/knowledge_centers/low-power/power-definitions/)
Definitions of terms related to power
# [Power Delivery Network (PDN)](https://semiengineering.com/knowledge_centers/low-power/power-delivery-network-pdn/)
Moving power around a device.
# [Power Estimation](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-estimation/)
How is power consumption estimated
# [Power Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/power-gating/)
Reducing power by turning off parts of a design
# [Power Gating Retention](https://semiengineering.com/knowledge_centers/low-power/techniques/power-gating/power-gating-retention/)
Special flop or latch used to retain the state of the cell when its main power supply is shut off.
# [Power Isolation](https://semiengineering.com/knowledge_centers/low-power/techniques/power-isolation/)
Addition of isolation cells around power islands
# [Power Issues](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/)
Power reduction at the architectural level
# [Power Management Coverage](https://semiengineering.com/knowledge_centers/low-power/power-management-coverage/)
Ensuring power control circuitry is fully verified
# [Power Management IC (PMIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-management-ic-pmic/)
An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.
# [Power MOSFETs](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/power-mosfets/)
A power semiconductor used to control and convert electric power.
# [Power Semiconductors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-semiconductors-power-ic/)
A power IC is used as a switch or rectifier in high voltage power applications.
# [Power Semiconductors Report: A Deep Dive Into Materials, Manufacturing & Business](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-semiconductors-power-ic/power-semiconductors-report-a-deep-dive-into-materials-manufacturing-business/)
# [Power Supply Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/power-supply-noise/)
Noise transmitted through the power delivery network
# [Power Switching](https://semiengineering.com/knowledge_centers/low-power/techniques/power-switching/)
Controlling power for power shutoff
# [Power Techniques](https://semiengineering.com/knowledge_centers/low-power/techniques/)
# [Power-Aware Design](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-aware-design/)
Techniques that analyze and optimize power in a design
# [Power-Aware Test](https://semiengineering.com/knowledge_centers/test/power-aware-test-2/)
Test considerations for low-power circuitry
# [PPA (Power, Performance, Area)](https://semiengineering.com/knowledge_centers/eda-design/definitions/ppa/)
Fundamental tradeoffs made in semiconductor design for power, performance and area.
# [Printed Circuit Board (PCB)](https://semiengineering.com/knowledge_centers/eda-design/definitions/printed-circuit-board/)
The design, verification, assembly and test of printed circuit boards
# [Process](https://semiengineering.com/knowledge_centers/manufacturing/process/)
# [Process Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/process-power-optimizations/)
power optimization techniques at the process level
# [Process Variation](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/variability/)
Variability in the semiconductor manufacturing process
# [Processor Utilization](https://semiengineering.com/knowledge_centers/eda-design/verification/processor-utilization/)
A measurement of the amount of time processor core(s) are actively in use.
# [Processors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/)
An integrated circuit or part of an IC that does logic and math processing.
# [Property Specification Language](https://semiengineering.com/knowledge_centers/languages/property-specification-language/)
Verification language based on formal specification of behavior
# [Quantum Computing](https://semiengineering.com/knowledge_centers/compute-architectures/quantum-computing/)
A different way of processing data using qubits.
# [Radio Frequency (RF)](https://semiengineering.com/knowledge_centers/data-movement/wireless/rf/)
Issues that pertain to Radio Frequency (RF) analog
# [Random Telegraph Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/random-telegraph-noise/)
Random trapping of charge carriers
# [Rapid Thermal Anneal (RTA), Rapid Thermal Processing (RTP)](https://semiengineering.com/knowledge_centers/manufacturing/process/rapid-thermal-anneal-rta-rapid-thermal-processing-rtp/)
The process of rapidly heating wafers.
# [Redistribution Layers (RDLs)](https://semiengineering.com/knowledge_centers/packaging/redistribution-layers-rdls/)
Copper metal interconnects that electrically connect one part of a package to another.
# [Regional Developments/Issues](https://semiengineering.com/knowledge_centers/regional-developments-issues/)
# [Reliability Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/reliability-verification/)
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.
# [ReRAM materials](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/resistive-ram/reram-materials/)
Materials used to manufacture ReRAMs
# [Resistive RAM (ReRAM/RRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/resistive-ram/)
Memory utilizing resistive hysteresis
# [Reticle](https://semiengineering.com/knowledge_centers/manufacturing/lithography/reticle/)
Synonymous with photomask.
# [Rich Interactive Test Database (RITdb)](https://semiengineering.com/knowledge_centers/test/data-analytics/rich-interactive-test-database-ritdb/)
A proposed test data standard aimed at reducing the burden for test engineers and test operations.
# [RISC-V](https://semiengineering.com/knowledge_centers/compute-architectures/risc-v/)
An open-source ISA used in designing integrated circuits at lower cost.
# [Root of Trust](https://semiengineering.com/knowledge_centers/semiconductor-security/root-of-trust/)
Trusted environment for secure functions.
# [RTL (Register Transfer Level)](https://semiengineering.com/knowledge_centers/eda-design/definitions/register-transfer-level/)
An abstraction for defining the digital portions of a design
# [RTL Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/rtl-power-optimizations/)
Optimization of power consumption at the Register Transfer Level
# [RTL Signoff](https://semiengineering.com/knowledge_centers/eda-design/verification/rtl-signoff/)
A series of requirements that must be met before moving past the RTL phase
# [RVM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/rvm/)
Verification methodology based on Vera
# [SAT Solver](https://semiengineering.com/knowledge_centers/eda-design/verification/sat-solver/)
Algorithm used to solve problems
# [Scan Test](https://semiengineering.com/knowledge_centers/test/scan-test-2/)
Additional logic that connects registers into a shift register or scan chain for increased test efficiency.
# [Scoreboard](https://semiengineering.com/knowledge_centers/eda-design/verification/scoreboard/)
Mechanism for storing stimulus in testbench
# [SCV SystemC Verification](https://semiengineering.com/knowledge_centers/standards-laws/standards/scv/)
Testbench support for SystemC
# [Self-Aligned Double Patterning (SADP)](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/self-aligned-double-patterning/)
A form of double patterning.
# [Semiconductor Manufacturing](https://semiengineering.com/knowledge_centers/manufacturing/)
Subjects related to the manufacture of semiconductors
# [Semiconductor Security](https://semiengineering.com/knowledge_centers/semiconductor-security/)
Methods and technologies for keeping data safe.
# [Sensor Fusion](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/sensor-fusion/)
Combining input from multiple sensor types.
# [Sensor Signal Conditioner (SSC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/sensor-signal-conditioner-ssc/)
An IC that conditions an analog sensor signal and converts to it digital before sending to a microcontroller.
# [Sensors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/)
Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.
# [serializer/deserializer (SerDes)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/serializer-deserializer-serdes/)
A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.
# [Shift Left](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/shift-left/)
In semiconductor development flow, tasks once performed sequentially must now be done concurrently.
# [Shmooing, Shmoo test, Shmoo plot](https://semiengineering.com/knowledge_centers/test/shmooing-shmoo-test-shmoo-plot/)
Sweeping a test condition parameter through a range and obtaining a plot of the results.
# [Short Channel Effects](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/short-channel-effects/)
When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.
# [Shot Noise](https://semiengineering.com/knowledge_centers/manufacturing/lithography/shot-noise/)
Quantization noise
# [Side Channel Attacks](https://semiengineering.com/knowledge_centers/semiconductor-security/side-channel-attacks/)
A class of attacks on a device and its contents by analyzing information using different access methods.
# [Silent Data Corruption (SDC)](https://semiengineering.com/knowledge_centers/test/silent-data-corruption-sdc/)
Undetected errors in data output from an integrated circuit.
# [Silicon Carbide (SiC)](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/silicon-carbide/)
A wide-bandgap technology used for FETs and MOSFETs for power transistors.
# [Silicon Photonics](https://semiengineering.com/knowledge_centers/data-movement/photonics/silicon-photonics/)
The integration of photonic devices into silicon
# [Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/)
A simulator exercises of model of hardware
# [Simulation Acceleration](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/simulation-acceleration/)
Special purpose hardware used to accelerate the simulation process.
# [Simultaneous Switching Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/simultaneous-switching-noise/)
Disturbance in ground voltage
# [Small Language Models (SLMs)](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/small-language-models-slms/)
# [Soft IP](https://semiengineering.com/knowledge_centers/intellectual-property/soft-ip/)
Synthesizable IP block
# [Software-Defined Vehicles (SDV)](https://semiengineering.com/knowledge_centers/automotive/software-defined-vehicles/)
# [Software-Driven Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/software-driven-verification/)
Verification methodology utilizing embedded processors
# [Software/Hardware Interface for Multicore/Manycore (SHIM) processors](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/softwarehardware-interface-for-multicoremanycore-shim-processors/)
Defines an architecture description useful for software design
# [SPICE](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/spice/)
Circuit Simulator first developed in the 70s
# [Spiking Neural Network (SNN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/spiking-neural-network-snn/)
A type of neural network that attempts to more closely model the brain.
# [Spin-Orbit Torque MRAM (SOT-MRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/spin-orbit-torque-mram-sot-mram/)
A type of MRAM with separate paths for write and read.
# [Standard Essential Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/standard-essential-patent/)
A patent that has been deemed necessary to implement a standard.
# [Standard Test Data Format (STDF)](https://semiengineering.com/knowledge_centers/test/data-analytics/standard-test-data-format-stdf/)
The most commonly used data format for semiconductor test information.
# [Standards](https://semiengineering.com/knowledge_centers/standards-laws/standards/)
Standards are important in any industry.
# [Standards & Laws](https://semiengineering.com/knowledge_centers/standards-laws/)
# [Startup Funding in China eBook: Notable investments in the semiconductor industry](https://semiengineering.com/knowledge_centers/regional-developments-issues/china/startup-funding-in-china-2022-ebook/)
# [Startups](https://semiengineering.com/knowledge_centers/startups/)
# [Static Random Access Memory (SRAM)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/static-random-access-memory/)
SRAM is a volatile memory that does not require refresh
# [Stimulus Constraints](https://semiengineering.com/knowledge_centers/eda-design/verification/stimulus-constraints/)
Constraints on the input to guide random generation process
# [Stochastics, Stochastic-Induced Defects](https://semiengineering.com/knowledge_centers/manufacturing/lithography/euv/stochastics-stochastic-induced-defects/)
Random variables that cause defects on chips during EUV lithography.
# [STT-MRAM](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/stt-mram/)
An advanced type of MRAM
# [Substrate Biasing](https://semiengineering.com/knowledge_centers/low-power/techniques/substrate-biasing/)
Use of Substrate Biasing
# [Substrate Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/substrate-noise/)
Coupling through the substrate.
# [System In Package (SiP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/system-in-package/)
A method for bundling multiple ICs to work together as a single chip.
# [System on Chip (SoC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/system-on-chip/)
A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor
# [SystemC](https://semiengineering.com/knowledge_centers/languages/systemc/)
A class library built on top of the C++ language used for modeling hardware
# [SystemC-AMS](https://semiengineering.com/knowledge_centers/languages/systemc-ams/)
Analog and mixed-signal extensions to SystemC
# [SystemVerilog](https://semiengineering.com/knowledge_centers/languages/systemverilog/)
Industry standard design and verification language
# [Tensor Processing Unit (TPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/tensor-processing-unit-tpu/)
Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.
# [Testbench](https://semiengineering.com/knowledge_centers/eda-design/verification/testbench/)
Software used to functionally verify a design
# [Thermal Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/thermal-noise/)
Noise related to heat
# [Through-Silicon Vias (TSVs)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/through-silicon-vias/)
Through-Silicon Vias are a technology to connect various die in a stacked die configuration.
# [Trace](https://semiengineering.com/knowledge_centers/test/trace/)
# [Transistors](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/)
Basic building block for both analog and digital integrated circuits.
# [Transition Rate Buffering](https://semiengineering.com/knowledge_centers/low-power/techniques/transition-rate-buffering-2/)
Minimizing switching times
# [Triple Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/triple-patterning/)
A multi-patterning technique that will be required at 10nm and below.
# [Tunnel FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/tunnel-fet/)
A type of transistor under development that could replace finFETs in future process technologies.
# [UL 4600 â Standard for Safety for the Evaluation of Autonomous Products](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/ul-4600-standard-for-safety-for-the-evaluation-of-autonomous-products/)
Standard for safety analysis and evaluation of autonomous vehicles.
# [Unified Coverage Interoperability Standard (Verification)](https://semiengineering.com/knowledge_centers/standards-laws/standards/unified-coverage-interoperability-standard/)
The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.
# [Unified Power Format (UPF)](https://semiengineering.com/knowledge_centers/standards-laws/standards/unified-power-format/)
Accellera Unified Power Format (UPF)
# [Universal Chiplet Interconnect Express (UCIe)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/universal-chiplet-interconnect-express-ucie/)
Die-to-die interconnect specification.
# [Universal Verification Methodology (UVM)](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/uvm/)
Verification methodology
# [URM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/urm/)
SystemVerilog version of eRM
# [User Interfaces](https://semiengineering.com/knowledge_centers/user-interfaces/)
User interfaces is the conduit a human uses to communicate with an electronics device.
# [Utility Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/utility-patent/)
Patent to protect an invention
# [Vera](https://semiengineering.com/knowledge_centers/languages/vera/)
Hardware Verification Language
# [Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/)
# [Verification IP (VIP)](https://semiengineering.com/knowledge_centers/intellectual-property/verification-ip-vip/)
A pre-packaged set of code used for verification.
# [Verification Methodologies](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/)
A standardized way to verify integrated circuit designs.
# [Verification Plan](https://semiengineering.com/knowledge_centers/eda-design/verification/verification-plan/)
A document that defines what functional verification is going to be performed
# [Verilog](https://semiengineering.com/knowledge_centers/languages/verilog/)
Hardware Description Language in use since 1984
# [Verilog Procedural Interface](https://semiengineering.com/knowledge_centers/languages/verilog/verilog-procedural-interface/)
Procedural access to Verilog objects
# [Verilog-AMS](https://semiengineering.com/knowledge_centers/standards-laws/standards/verilog-ams/)
Analog extensions to Verilog
# [VHDL](https://semiengineering.com/knowledge_centers/languages/vhdl/)
Hardware Description Language
# [Virtual Prototype](https://semiengineering.com/knowledge_centers/eda-design/verification/virtual-prototype/)
An abstract model of a hardware system enabling early software execution.
# [VMM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/vmm/)
Verification methodology built by Synopsys
# [Voice control, speech recognition, voice-user interface (VUI)](https://semiengineering.com/knowledge_centers/user-interfaces/voice-control-speech-recognition-voice-user-interface-vui/)
Using voice/speech for device command and control.
# [Volatile Memory](https://semiengineering.com/knowledge_centers/memory/volatile-memory/)
Memory that loses storage abilities when power is removed.
# [Voltage Islands](https://semiengineering.com/knowledge_centers/low-power/techniques/voltage-islands/)
Use of multiple voltages for power reduction
# [Von Neumann Architecture](https://semiengineering.com/knowledge_centers/compute-architectures/von-neumann-architecture/)
The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.
# [Wafer Fab Testing](https://semiengineering.com/knowledge_centers/test/wafer-fab-testing/)
Verifying and testing the dies on the wafer after the manufacturing.
# [Wafer Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/)
The science of finding defects on a silicon wafer.
# [Wi-Fi](https://semiengineering.com/knowledge_centers/data-movement/wireless/wi-fi/)
A brand name for a group of wireless networking protocols and technology,
# [Wide I/O: memory interface standard for 3D IC](https://semiengineering.com/knowledge_centers/standards-laws/standards/wide-io-2/)
3D memory interface standard
# [Wirebonding](https://semiengineering.com/knowledge_centers/packaging/wirebonding/)
Creating interconnects between IC and package using a thin wire.
# [Wireless](https://semiengineering.com/knowledge_centers/data-movement/wireless/)
A way of moving data without wires.
# [X Architecture](https://semiengineering.com/knowledge_centers/low-power/techniques/x-architecture/)
IC interconnect architecture
# [X Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/x-verification/)
X Propagation causes problems
# [Yield Management System (YMS)](https://semiengineering.com/knowledge_centers/manufacturing/yield-management-system-yms/)
A data-driven system for monitoring and improving IC yield and reliability.
# [Zero-Day Vulnerabilities, Attacks](https://semiengineering.com/knowledge_centers/semiconductor-security/zero-day-vulnerabilities-attacks/)
A vulnerability in a productâs hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.
# [Zonal Architectures](https://semiengineering.com/knowledge_centers/automotive/zonal-architectures/)
# [Aart de Geus](https://semiengineering.com/people/aart-de-geus/)
# [Adam Kablanian](https://semiengineering.com/people/adam-kablanian/)
# [Aditya Mittal](https://semiengineering.com/people/aditya-mittal/)
# [Adnan Hamid](https://semiengineering.com/people/adnan-hamid/)
# [Adrian Simionescu](https://semiengineering.com/people/adrian-simionescu/)
# [Ahmed Hemani](https://semiengineering.com/people/ahmed-hemani/)
# [Ajay Daga](https://semiengineering.com/people/ajay-daga/)
# [Ajoy K. Bose](https://semiengineering.com/people/ajoy-k-bose/)
# [Akash Deshpande](https://semiengineering.com/people/akash-deshpande/)
# [Aki Fujimura](https://semiengineering.com/people/aki-fujimura/)
# [Al Akermann](https://semiengineering.com/people/al-akermann/)
# [Alain Fanet](https://semiengineering.com/people/alain-fanet/)
# [Alain J. Hanover](https://semiengineering.com/people/alain-j-hanover/)
# [Alakesh Chetia](https://semiengineering.com/people/alakesh-chetia/)
# [Alan Scott](https://semiengineering.com/people/alan-scott/)
# [Alberto Sangiovanni-Vincentelli](https://semiengineering.com/people/alberto-sangiovanni-vincentelli/)
# [Alex Alexanian](https://semiengineering.com/people/alex-alexanian/)
# [Alexander Samoylov](https://semiengineering.com/people/alexander-samoylov/)
# [Alisa Yaffa](https://semiengineering.com/people/alisa-yaffa/)
# [Allan Douglas](https://semiengineering.com/people/allan-douglas/)
# [Amir Zarkesh](https://semiengineering.com/people/amir-zarkesh/)
# [Amit Gupta](https://semiengineering.com/people/amit-gupta/)
# [Amit Mehrotra](https://semiengineering.com/people/amit-mehrotra/)
# [Amit Narayan](https://semiengineering.com/people/amit-narayan/)
# [Amit Saxena](https://semiengineering.com/people/amit-saxena/)
# [Amr Mohsen](https://semiengineering.com/people/amr-mohsen/)
# [An-Chang Deng](https://semiengineering.com/people/an-chang-deng/)
# [An-Yu Kuo](https://semiengineering.com/people/an-yu-kuo/)
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# [Devadas Varma](https://semiengineering.com/people/devadas-varma/)
# [Devesh Guatam](https://semiengineering.com/people/devesh-guatam/)
# [Diana Marculescu](https://semiengineering.com/people/diana-marculescu/)
# [Dirk Lanneer](https://semiengineering.com/people/dirk-lanneer/)
# [Dominik Strasser](https://semiengineering.com/people/dominik-strasser/)
# [Don Emil Pezzolo](https://semiengineering.com/people/don-emil-pezzolo/)
# [Don McInnis](https://semiengineering.com/people/don-mcinnis/)
# [Don-Min Tsou](https://semiengineering.com/people/don-min-tsou/)
# [Donald Bennett](https://semiengineering.com/people/donald-bennett/)
# [Doug Fairbairn](https://semiengineering.com/people/doug-fairbairn/)
# [Drew E. Wingard](https://semiengineering.com/people/drew-e-wingard/)
# [Duncan Bremner](https://semiengineering.com/people/duncan-bremner/)
# [Durga Lakshmi Sangisetti](https://semiengineering.com/people/durga-lakshmi-sangisetti/)
# [Ed Blackmond](https://semiengineering.com/people/ed-blackmond/)
# [Edmund K. Cheng](https://semiengineering.com/people/edmund-k-cheng/)
# [Edvard Sørgürd](https://semiengineering.com/people/edvard-sa%C2%B8rga%C2%A5rd/)
# [Edward A. Lee](https://semiengineering.com/people/edward-a-lee/)
# [Edward Komp](https://semiengineering.com/people/edward-komp/)
# [Edward N. Evans](https://semiengineering.com/people/edward-n-evans/)
# [Egino Sarto](https://semiengineering.com/people/egino-sarto/)
# [Elena Potanina](https://semiengineering.com/people/elena-potanina/)
# [Eli Yablonovitch](https://semiengineering.com/people/eli-yablonovitch/)
# [Ellis Smith](https://semiengineering.com/people/ellis-smith/)
# [Enno Wein](https://semiengineering.com/people/enno-wein/)
# [Eric Ryherd](https://semiengineering.com/people/eric-ryherd/)
# [Eric Beisser](https://semiengineering.com/people/eric-beisser/)
# [Eric Dormer](https://semiengineering.com/people/eric-dormer/)
# [Eric Dupont](https://semiengineering.com/people/eric-dupont/)
# [Eric Dupont-Nivet](https://semiengineering.com/people/eric-dupont-nivet/)
# [Eric Peers](https://semiengineering.com/people/eric-peers/)
# [Eric T. Hennenhoefer](https://semiengineering.com/people/eric-t-hennenhoefer/)
# [Erik Lauwers](https://semiengineering.com/people/erik-lauwers/)
# [Esin Terzioglu](https://semiengineering.com/people/esin-terzioglu/)
# [Eun Sei Park](https://semiengineering.com/people/eun-sei-park/)
# [Ewald Detjens](https://semiengineering.com/people/ewald-detjens/)
# [Fadil Kotaji](https://semiengineering.com/people/fadil-kotaji/)
# [Fang-Cheng Chang](https://semiengineering.com/people/fang-cheng-chang/)
# [Fang-Li Yuan](https://semiengineering.com/people/fang-li-yuan/)
# [Farakh Javid](https://semiengineering.com/people/farakh-javid/)
# [Fergus Slorach](https://semiengineering.com/people/fergus-slorach/)
# [Fia Johansson](https://semiengineering.com/people/fia-johansson/)
# [Firas Mohamed](https://semiengineering.com/people/firas-mohamed/)
# [Founder(s) Unknown](https://semiengineering.com/people/founders-unknown/)
# [François Constant](https://semiengineering.com/people/frana%C2%A7ois-constant/)
# [Francis Bernard](https://semiengineering.com/people/francis-bernard/)
# [Frank Gennari](https://semiengineering.com/people/frank-gennari/)
# [Frank Costa](https://semiengineering.com/people/frank-costa/)
# [Frank DeRemer](https://semiengineering.com/people/frank-deremer/)
# [Frank Schenkel](https://semiengineering.com/people/frank-schenkel/)
# [Franz Dugand](https://semiengineering.com/people/franz-dugand/)
# [Frederic Reblewski](https://semiengineering.com/people/frederic-reblewski/)
# [Frederick (Fred) Saal](https://semiengineering.com/people/frederick-fred-saal/)
# [Fuad Musa](https://semiengineering.com/people/fuad-musa/)
# [Fumiaki Sato](https://semiengineering.com/people/fumiaki-sato/)
# [Gabi Leshem](https://semiengineering.com/people/gabi-leshem/)
# [Gagan Hasteer](https://semiengineering.com/people/gagan-hasteer/)
# [Ganapathy Subramaniam](https://semiengineering.com/people/ganapathy-subramaniam/)
# [Gene Dancause](https://semiengineering.com/people/gene-dancause/)
# [Gene Marsh](https://semiengineering.com/people/gene-marsh/)
# [Geoffrey Tate](https://semiengineering.com/people/geoffrey-tate/)
# [Gerald H. Langeler](https://semiengineering.com/people/gerald-h-langeler/)
# [Gerald L (Jerry) Frenkil](https://semiengineering.com/people/gerald-l-jerry-frenkil/)
# [Gerald Pechanek](https://semiengineering.com/people/gerald-pechanek/)
# [Gerhard Angst](https://semiengineering.com/people/gerhard-angst/)
# [Gert Goossens](https://semiengineering.com/people/gert-goossens/)
# [Ghassan (Gus) Y. Yacoub](https://semiengineering.com/people/ghassan-gus-y-yacoub/)
# [Ghislain Kaiser](https://semiengineering.com/people/ghislain-kaiser/)
# [Giacinto Paolo Saggese](https://semiengineering.com/people/giacinto-paolo-saggese/)
# [Gil Winograd](https://semiengineering.com/people/gil-winograd/)
# [Glen M. Antle](https://semiengineering.com/people/glen-m-antle/)
# [Gopa Periyadan](https://semiengineering.com/people/gopa-periyadan/)
# [Gopal Krishna Nayak](https://semiengineering.com/people/gopal-krishna-nayak/)
# [Gordon B. Hoffman](https://semiengineering.com/people/gordon-b-hoffman/)
# [Gordon Baty](https://semiengineering.com/people/gordon-baty/)
# [Gordon E. Moore](https://semiengineering.com/people/gordon-e-moore/)
# [Graham Hellestrand](https://semiengineering.com/people/graham-hellestrand/)
# [Grant A. Pierce](https://semiengineering.com/people/grant-a-pierce/)
# [Greg Doyle](https://semiengineering.com/people/greg-doyle/)
# [Greg Hoeppner](https://semiengineering.com/people/greg-hoeppner/)
# [Greg Lloyd](https://semiengineering.com/people/greg-lloyd/)
# [Greg M. Ordy](https://semiengineering.com/people/greg-m-ordy/)
# [Gregory Recupero](https://semiengineering.com/people/gregory-recupero/)
# [Guido Arnout](https://semiengineering.com/people/guido-arnout/)
# [GĂźnter Keil](https://semiengineering.com/people/ga%C2%BCnter-keil/)
# [Guy Bois](https://semiengineering.com/people/guy-bois/)
# [Guy de Burgh](https://semiengineering.com/people/guy-de-burgh/)
# [Hal Alles](https://semiengineering.com/people/hal-alles/)
# [Hal Conklin](https://semiengineering.com/people/hal-conklin/)
# [Hamid Savoj](https://semiengineering.com/people/hamid-savoj/)
# [Harald Neubauer](https://semiengineering.com/people/harald-neubauer/)
# [Hardeep Gulati](https://semiengineering.com/people/hardeep-gulati/)
# [Harm Arts](https://semiengineering.com/people/harm-arts/)
# [HarnHua Ng](https://semiengineering.com/people/harnhua-ng/)
# [Harvey C. Jones jr.](https://semiengineering.com/people/harvey-c-jones-jr/)
# [Hayder Mrabet](https://semiengineering.com/people/hayder-mrabet/)
# [Hazem El Tahawy](https://semiengineering.com/people/hazem-el-tahawy/)
# [Hein van der Wildt](https://semiengineering.com/people/hein-van-der-wildt/)
# [Heinrich Meyr](https://semiengineering.com/people/heinrich-meyr/)
# [Helmut Gräb](https://semiengineering.com/people/helmut-gra%C2%A4b/)
# [Helmut Mahr](https://semiengineering.com/people/helmut-mahr/)
# [Henrik Pallisgaard](https://semiengineering.com/people/henrik-pallisgaard/)
# [Henry Cox](https://semiengineering.com/people/henry-cox/)
# [Hermann Hauser](https://semiengineering.com/people/hermann-hauser/)
# [Hiro Moriyasu](https://semiengineering.com/people/hiro-moriyasu/)
# [Holly Stump](https://semiengineering.com/people/holly-stump/)
# [Howard L. Martin](https://semiengineering.com/people/howard-l-martin/)
# [Howard Pakosh](https://semiengineering.com/people/howard-pakosh/)
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# [Ian Page](https://semiengineering.com/people/ian-page/)
# [Ian Tsybulkin](https://semiengineering.com/people/ian-tsybulkin/)
# [Ihao Chen](https://semiengineering.com/people/ihao-chen/)
# [Ivan Pesic](https://semiengineering.com/people/ivan-pesic/)
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# [J. George Janac](https://semiengineering.com/people/j-george-janac/)
# [Jack Herrick](https://semiengineering.com/people/jack-herrick/)
# [Jack Harding](https://semiengineering.com/people/jack-harding/)
# [Jack Little](https://semiengineering.com/people/jack-little/)
# [Jack Peng](https://semiengineering.com/people/jack-peng/)
# [Jacob Ben-Meir](https://semiengineering.com/people/jacob-ben-meir/)
# [James (Jim) Fiske](https://semiengineering.com/people/james-jim-fiske/)
# [James (Jim) Ready](https://semiengineering.com/people/james-jim-ready/)
# [James B. Morris](https://semiengineering.com/people/james-b-morris/)
# [James C. Rautio](https://semiengineering.com/people/james-c-rautio/)
# [James E. (Jim) Solomon](https://semiengineering.com/people/james-e-jim-solomon/)
# [James G. Crocker](https://semiengineering.com/people/james-g-crocker/)
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# [James Truchard](https://semiengineering.com/people/james-truchard/)
# [James V Barnett II](https://semiengineering.com/people/james-v-barnett-ii/)
# [Jamsheed Agahi](https://semiengineering.com/people/jamsheed-agahi/)
# [Janak H. Patel](https://semiengineering.com/people/janak-h-patel/)
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# [Jason Campbell](https://semiengineering.com/people/jason-campbell/)
# [Jason Cong](https://semiengineering.com/people/jason-cong/)
# [Jason Xing](https://semiengineering.com/people/jason-xing/)
# [Jauher Zaidi](https://semiengineering.com/people/jauher-zaidi/)
# [Jaushin Lee](https://semiengineering.com/people/jaushin-lee/)
# [Jay Avula](https://semiengineering.com/people/jay-avula/)
# [Jean Barbier](https://semiengineering.com/people/jean-barbier/)
# [Jean Brouwers](https://semiengineering.com/people/jean-brouwers/)
# [Jean-Luc Pelloie](https://semiengineering.com/people/jean-luc-pelloie/)
# [Jean-Philippe Lambert](https://semiengineering.com/people/jean-philippe-lambert/)
# [Jean-Pierre Appel](https://semiengineering.com/people/jean-pierre-appel/)
# [Jean-Pierre Lecailliez](https://semiengineering.com/people/jean-pierre-lecailliez/)
# [Jean-Yves Brena](https://semiengineering.com/people/jean-yves-brena/)
# [Jeff Fox](https://semiengineering.com/people/jeff-fox/)
# [Jeff Bier](https://semiengineering.com/people/jeff-bier/)
# [Jeff Galloway](https://semiengineering.com/people/jeff-galloway/)
# [Jeff Kodosky](https://semiengineering.com/people/jeff-kodosky/)
# [Jeff Tuan](https://semiengineering.com/people/jeff-tuan/)
# [Jens C. Michelsen](https://semiengineering.com/people/jens-c-michelsen/)
# [Jens J. Tybo Jensen](https://semiengineering.com/people/jens-j-tybo-jensen/)
# [Jens P. Tagore-Brage](https://semiengineering.com/people/jens-p-tagore-brage/)
# [Jeong-Tyng Li](https://semiengineering.com/people/jeong-tyng-li/)
# [Jeremy Birch](https://semiengineering.com/people/jeremy-birch/)
# [Jerome Vanthournout](https://semiengineering.com/people/jerome-vanthournout/)
# [Jesper Knudsen](https://semiengineering.com/people/jesper-knudsen/)
# [Jez San](https://semiengineering.com/people/jez-san/)
# [Jian X. Zheng](https://semiengineering.com/people/jian-x-zheng/)
# [Jim McCanny](https://semiengineering.com/people/jim-mccanny/)
# [Jim Sansbury](https://semiengineering.com/people/jim-sansbury/)
# [Jinsong Zhao](https://semiengineering.com/people/jinsong-zhao/)
# [Joe Higgins](https://semiengineering.com/people/joe-higgins/)
# [Joe Tanous](https://semiengineering.com/people/joe-tanous/)
# [Joe Tatham](https://semiengineering.com/people/joe-tatham/)
# [Joerg Grosse](https://semiengineering.com/people/joerg-grosse/)
# [Joey Y. Lin](https://semiengineering.com/people/joey-y-lin/)
# [Johan Van Praet](https://semiengineering.com/people/johan-van-praet/)
# [Johan Peeters](https://semiengineering.com/people/johan-peeters/)
# [Johann Foucher](https://semiengineering.com/people/johann-foucher/)
# [Johannes Emigholz](https://semiengineering.com/people/johannes-emigholz/)
# [John Gilbert](https://semiengineering.com/people/john-gilbert/)
# [John A. Swanson](https://semiengineering.com/people/john-a-swanson/)
# [John Charles Carveth](https://semiengineering.com/people/john-charles-carveth/)
# [John Croix](https://semiengineering.com/people/john-croix/)
# [John Durbetaki](https://semiengineering.com/people/john-durbetaki/)
# [John F. Cooper](https://semiengineering.com/people/john-f-cooper/)
# [John Goodenough](https://semiengineering.com/people/john-goodenough/)
# [John Halfpenny](https://semiengineering.com/people/john-halfpenny/)
# [John Hall](https://semiengineering.com/people/john-hall/)
# [John Hatfield](https://semiengineering.com/people/john-hatfield/)
# [john Judkins](https://semiengineering.com/people/john-judkins/)
# [John K. Kibarian](https://semiengineering.com/people/john-k-kibarian/)
# [John Lee](https://semiengineering.com/people/john-lee/)
# [John Lofton Holt](https://semiengineering.com/people/john-lofton-holt/)
# [John Maneatis](https://semiengineering.com/people/john-maneatis/)
# [John Mills](https://semiengineering.com/people/john-mills/)
# [John Ott](https://semiengineering.com/people/john-ott/)
# [John R. Maticich](https://semiengineering.com/people/john-r-maticich/)
# [John Sanguinetti](https://semiengineering.com/people/john-sanguinetti/)
# [John Tanner](https://semiengineering.com/people/john-tanner/)
# [Johnathan Weiss](https://semiengineering.com/people/johnathan-weiss/)
# [Johnson Limqueco](https://semiengineering.com/people/johnson-limqueco/)
# [Jonathan Cagan](https://semiengineering.com/people/jonathan-cagan/)
# [Jonathan Rose](https://semiengineering.com/people/jonathan-rose/)
# [Jordan Swartz](https://semiengineering.com/people/jordan-swartz/)
# [Joseph Skazinski](https://semiengineering.com/people/joseph-skazinski/)
# [Joseph B. Costello](https://semiengineering.com/people/joseph-b-costello/)
# [Joseph E. Pekarek](https://semiengineering.com/people/joseph-e-pekarek/)
# [Joseph Lee](https://semiengineering.com/people/joseph-lee/)
# [Joseph Rothman](https://semiengineering.com/people/joseph-rothman/)
# [Josh Lee](https://semiengineering.com/people/josh-lee/)
# [Juliusz Poltz](https://semiengineering.com/people/juliusz-poltz/)
# [Jun-Jyeh Hsiao](https://semiengineering.com/people/jun-jyeh-hsiao/)
# [Jørn Nystad](https://semiengineering.com/people/ja%C2%B8rn-nystad/)
# [K. Charles Janac](https://semiengineering.com/people/k-charles-janac/)
# [K.C. Shih](https://semiengineering.com/people/k-c-shih/)
# [Kaiwin Lee](https://semiengineering.com/people/kaiwin-lee/)
# [Kamran Elahian](https://semiengineering.com/people/kamran-elahian/)
# [Kannankote Sriram](https://semiengineering.com/people/kannankote-sriram/)
# [Karel Masarik](https://semiengineering.com/people/karel-masarik/)
# [Karen Vahtra](https://semiengineering.com/people/karen-vahtra/)
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# [Keith Short](https://semiengineering.com/people/keith-short/)
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# [Keith Whisnant](https://semiengineering.com/people/keith-whisnant/)
# [Ken McElvain](https://semiengineering.com/people/ken-mcelvain/)
# [Ken Matusow](https://semiengineering.com/people/ken-matusow/)
# [Ken Seymour](https://semiengineering.com/people/ken-seymour/)
# [Ken Tseng](https://semiengineering.com/people/ken-tseng/)
# [Kenneth L. Shepard](https://semiengineering.com/people/kenneth-l-shepard/)
# [Kevin Chou](https://semiengineering.com/people/kevin-chou/)
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# [Kevin Ladd](https://semiengineering.com/people/kevin-ladd/)
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# [Luc Burgun](https://semiengineering.com/people/luc-burgun/)
# [Lucio Lanza](https://semiengineering.com/people/lucio-lanza/)
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# [Mark Hampton](https://semiengineering.com/people/mark-hampton/)
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# [Mark Olen](https://semiengineering.com/people/mark-olen/)
# [Mark R. Templeton](https://semiengineering.com/people/mark-r-templeton/)
# [Mark Santoro](https://semiengineering.com/people/mark-santoro/)
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# [Mark-Eric Jones](https://semiengineering.com/people/mark-eric-jones/)
# [Markus Mergens](https://semiengineering.com/people/markus-mergens/)
# [Marleen Boonen](https://semiengineering.com/people/marleen-boonen/)
# [Martin Baechtold](https://semiengineering.com/people/martin-baechtold/)
# [Martin Langhammer](https://semiengineering.com/people/martin-langhammer/)
# [Martin Lefebvre](https://semiengineering.com/people/martin-lefebvre/)
# [Martin Walker](https://semiengineering.com/people/martin-walker/)
# [Martin Wilson](https://semiengineering.com/people/martin-wilson/)
# [Mathias Silvant](https://semiengineering.com/people/mathias-silvant/)
# [Maurice Whelan](https://semiengineering.com/people/maurice-whelan/)
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# [Mel Gilmore](https://semiengineering.com/people/mel-gilmore/)
# [Michael McNamara](https://semiengineering.com/people/michael-mcnamara/)
# [Michael Alam](https://semiengineering.com/people/michael-alam/)
# [Michael Burstein](https://semiengineering.com/people/michael-burstein/)
# [Michael D. Hoyt](https://semiengineering.com/people/michael-d-hoyt/)
# [Michael Goldstone](https://semiengineering.com/people/michael-goldstone/)
# [Michael J. Jamiolkowski](https://semiengineering.com/people/michael-j-jamiolkowski/)
# [Michael Magranet](https://semiengineering.com/people/michael-magranet/)
# [Michael Nicolaidis](https://semiengineering.com/people/michael-nicolaidis/)
# [Michael Pronath](https://semiengineering.com/people/michael-pronath/)
# [Michael Wakim](https://semiengineering.com/people/michael-wakim/)
# [Michel Oger](https://semiengineering.com/people/michel-oger/)
# [Mike Rieger](https://semiengineering.com/people/mike-rieger/)
# [Mike Bartley](https://semiengineering.com/people/mike-bartley/)
# [Mike Borza](https://semiengineering.com/people/mike-borza/)
# [Mike Chandler](https://semiengineering.com/people/mike-chandler/)
# [Mike Dini](https://semiengineering.com/people/mike-dini/)
# [Mike Farmwald](https://semiengineering.com/people/mike-farmwald/)
# [Mike Kliment](https://semiengineering.com/people/mike-kliment/)
# [Mike Lee](https://semiengineering.com/people/mike-lee/)
# [Mike Meredith](https://semiengineering.com/people/mike-meredith/)
# [Mike Scase](https://semiengineering.com/people/mike-scase/)
# [Mike Yungho Tsai](https://semiengineering.com/people/mike-yungho-tsai/)
# [Mikko Varpiola](https://semiengineering.com/people/mikko-varpiola/)
# [Milton R. Smith](https://semiengineering.com/people/milton-r-smith/)
# [Misha Burich](https://semiengineering.com/people/misha-burich/)
# [Mohamed Kassem](https://semiengineering.com/people/mohamed-kassem/)
# [Mohan R](https://semiengineering.com/people/mohan-r/)
# [Mojy Chian](https://semiengineering.com/people/mojy-chian/)
# [Morris Chang](https://semiengineering.com/people/morris-chang/)
# [Murat Alaybeyi](https://semiengineering.com/people/murat-alaybeyi/)
# [Mustafa Celik](https://semiengineering.com/people/mustafa-celik/)
# [Naeem Zafar](https://semiengineering.com/people/naeem-zafar/)
# [Nagesh Gupta](https://semiengineering.com/people/nagesh-gupta/)
# [Naveed Sherwani](https://semiengineering.com/people/naveed-sherwani/)
# [Naveen Chava](https://semiengineering.com/people/naveen-chava/)
# [Neil Johnson](https://semiengineering.com/people/neil-johnson/)
# [Neil Roberts](https://semiengineering.com/people/neil-roberts/)
# [Nick Cobb](https://semiengineering.com/people/nick-cobb/)
# [Nick Martin](https://semiengineering.com/people/nick-martin/)
# [Nick Martin](https://semiengineering.com/people/nick-martin-2/)
# [Nicky Lu](https://semiengineering.com/people/nicky-lu/)
# [Nicolas Delorme](https://semiengineering.com/people/nicolas-delorme/)
# [Ning Nan](https://semiengineering.com/people/ning-nan/)
# [Noah Sturcken](https://semiengineering.com/people/noah-sturcken/)
# [Norman Chang](https://semiengineering.com/people/norman-chang/)
# [Ole Christian Andersen](https://semiengineering.com/people/ole-christian-andersen/)
# [Olivier Lepape](https://semiengineering.com/people/olivier-lepape/)
# [Ori Braun](https://semiengineering.com/people/ori-braun/)
# [Oscar Buset](https://semiengineering.com/people/oscar-buset/)
# [P.T. Patel](https://semiengineering.com/people/p-t-patel/)
# [Pascal Peru](https://semiengineering.com/people/pascal-peru/)
# [Patrick J. Ready](https://semiengineering.com/people/patrick-j-ready/)
# [Paul Cunningham](https://semiengineering.com/people/paul-cunningham/)
# [Paul (Yen-Son) Huang](https://semiengineering.com/people/paul-yen-son-huang/)
# [Paul de Dood](https://semiengineering.com/people/paul-de-dood/)
# [Paul Harvell](https://semiengineering.com/people/paul-harvell/)
# [Paul Johnson](https://semiengineering.com/people/paul-johnson/)
# [Paul Levine](https://semiengineering.com/people/paul-levine/)
# [Paul Lindermann](https://semiengineering.com/people/paul-lindermann/)
# [Paul M. Hubbard](https://semiengineering.com/people/paul-m-hubbard/)
# [Paul Newhagen](https://semiengineering.com/people/paul-newhagen/)
# [Paul Nguon](https://semiengineering.com/people/paul-nguon/)
# [Paul Rodman](https://semiengineering.com/people/paul-rodman/)
# [Paul van Besouw](https://semiengineering.com/people/paul-van-besouw/)
# [Paul Wells](https://semiengineering.com/people/paul-wells/)
# [Peer Schmitt](https://semiengineering.com/people/peer-schmitt/)
# [Pengwei Qian](https://semiengineering.com/people/pengwei-qian/)
# [Pete Popov](https://semiengineering.com/people/pete-popov/)
# [Peter Eichenberger](https://semiengineering.com/people/peter-eichenberger/)
# [Peter Denyer](https://semiengineering.com/people/peter-denyer/)
# [Peter Flake](https://semiengineering.com/people/peter-flake/)
# [Peter Ivey](https://semiengineering.com/people/peter-ivey/)
# [Peter Meuris](https://semiengineering.com/people/peter-meuris/)
# [Peter Odryna](https://semiengineering.com/people/peter-odryna/)
# [Peter Petrov](https://semiengineering.com/people/peter-petrov/)
# [Peter Rip](https://semiengineering.com/people/peter-rip/)
# [Petro Estakhri](https://semiengineering.com/people/petro-estakhri/)
# [Phil Moorby](https://semiengineering.com/people/phil-moorby/)
# [Phil Tharp](https://semiengineering.com/people/phil-tharp/)
# [Philippe Boucard](https://semiengineering.com/people/philippe-boucard/)
# [Philippe Diehl](https://semiengineering.com/people/philippe-diehl/)
# [Philippe Duchene](https://semiengineering.com/people/philippe-duchene/)
# [Pierre Marty](https://semiengineering.com/people/pierre-marty/)
# [Prab Varma](https://semiengineering.com/people/prab-varma/)
# [Prabhat Aggarwal](https://semiengineering.com/people/prabhat-aggarwal/)
# [Prabhu Goel](https://semiengineering.com/people/prabhu-goel/)
# [Pradeep Fernandes](https://semiengineering.com/people/pradeep-fernandes/)
# [Pradeep Vajram](https://semiengineering.com/people/pradeep-vajram/)
# [Prakash Narain](https://semiengineering.com/people/prakash-narain/)
# [Pravin Madhani](https://semiengineering.com/people/pravin-madhani/)
# [R. Dean Adams](https://semiengineering.com/people/r-dean-adams/)
# [R. Mark Gogolewski](https://semiengineering.com/people/r-mark-gogolewski/)
# [R.K. Patil](https://semiengineering.com/people/r-k-patil/)
# [Raghavendra Mohan V](https://semiengineering.com/people/raghavendra-mohan-v/)
# [Raik Brinkmann](https://semiengineering.com/people/raik-brinkmann/)
# [Raj Raghavan](https://semiengineering.com/people/raj-raghavan/)
# [Rajeev Madhavan](https://semiengineering.com/people/rajeev-madhavan/)
# [Rajendran (Raj) Nair](https://semiengineering.com/people/rajendran-raj-nair/)
# [Rajit Manohar](https://semiengineering.com/people/rajit-manohar/)
# [Rajit Chandra](https://semiengineering.com/people/rajit-chandra/)
# [Rajiv Kumar](https://semiengineering.com/people/rajiv-kumar/)
# [Ralf Huuck](https://semiengineering.com/people/ralf-huuck/)
# [Ram S. Ramanujam](https://semiengineering.com/people/ram-s-ramanujam/)
# [Ramin Hojati](https://semiengineering.com/people/ramin-hojati/)
# [Ramy Iskander](https://semiengineering.com/people/ramy-iskander/)
# [Randy Eager](https://semiengineering.com/people/randy-eager/)
# [Randy Allen](https://semiengineering.com/people/randy-allen/)
# [Randy Caplan](https://semiengineering.com/people/randy-caplan/)
# [Randy Deffert](https://semiengineering.com/people/randy-deffert/)
# [Randy Rhea](https://semiengineering.com/people/randy-rhea/)
# [Raul Camposano](https://semiengineering.com/people/raul-camposano/)
# [Rauli Kaksonen](https://semiengineering.com/people/rauli-kaksonen/)
# [Ravender Goyal](https://semiengineering.com/people/ravender-goyal/)
# [Ravi Mehta](https://semiengineering.com/people/ravi-mehta/)
# [Ravi Shankar Rao](https://semiengineering.com/people/ravi-shankar-rao/)
# [Ravi Thummarukudy](https://semiengineering.com/people/ravi-thummarukudy/)
# [Ray Bulgar](https://semiengineering.com/people/ray-bulgar/)
# [Raymond Turin](https://semiengineering.com/people/raymond-turin/)
# [Reinhard Keil](https://semiengineering.com/people/reinhard-keil/)
# [RĂŠmi Butaud](https://semiengineering.com/people/rami-butaud/)
# [Rhonda Dirvin](https://semiengineering.com/people/rhonda-dirvin/)
# [Rich Witek](https://semiengineering.com/people/rich-witek/)
# [Richard C. (Dick) Foss](https://semiengineering.com/people/richard-c-dick-foss/)
# [Richard Chang](https://semiengineering.com/people/richard-chang/)
# [Richard Doherty](https://semiengineering.com/people/richard-doherty/)
# [Richard Meacham](https://semiengineering.com/people/richard-meacham/)
# [Richard Rudell](https://semiengineering.com/people/richard-rudell/)
# [Richard Taylor](https://semiengineering.com/people/richard-taylor/)
# [Richard Weber](https://semiengineering.com/people/richard-weber/)
# [Rick Carlson](https://semiengineering.com/people/rick-carlson/)
# [Rick Lazansky](https://semiengineering.com/people/rick-lazansky/)
# [Rob A. Rutenbar](https://semiengineering.com/people/rob-a-rutenbar/)
# [Rob Dekker](https://semiengineering.com/people/rob-dekker/)
# [Rob Gowin](https://semiengineering.com/people/rob-gowin/)
# [Robert Harland](https://semiengineering.com/people/robert-harland/)
# [Robert Kurshan](https://semiengineering.com/people/robert-kurshan/)
# [Robert Blackburn](https://semiengineering.com/people/robert-blackburn/)
# [Robert H. Dennard](https://semiengineering.com/people/robert-h-dennard/)
# [Robert Hartmann](https://semiengineering.com/people/robert-hartmann/)
# [Robert Noyce](https://semiengineering.com/people/robert-noyce/)
# [Robert Smith](https://semiengineering.com/people/robert-smith/)
# [Robi Dutta](https://semiengineering.com/people/robi-dutta/)
# [Roger Sturgeon](https://semiengineering.com/people/roger-sturgeon/)
# [Roger Gook](https://semiengineering.com/people/roger-gook/)
# [Ron Maxwell](https://semiengineering.com/people/ron-maxwell/)
# [Ronald A. Rohrer](https://semiengineering.com/people/ronald-a-rohrer/)
# [Ross Feeman](https://semiengineering.com/people/ross-feeman/)
# [Roy Prasad](https://semiengineering.com/people/roy-prasad/)
# [Sagar Reddy](https://semiengineering.com/people/sagar-reddy/)
# [Sailesh Kumar](https://semiengineering.com/people/sailesh-kumar/)
# [Sally Shlaer](https://semiengineering.com/people/sally-shlaer/)
# [Salvatore Carcia](https://semiengineering.com/people/salvatore-carcia/)
# [Sam Appleton](https://semiengineering.com/people/sam-appleton/)
# [Sam Kim](https://semiengineering.com/people/sam-kim/)
# [Samir Shroff](https://semiengineering.com/people/samir-shroff/)
# [Sandeep Srinivasan](https://semiengineering.com/people/sandeep-srinivasan/)
# [Sandipan Bhanot](https://semiengineering.com/people/sandipan-bhanot/)
# [Sang S. Wang](https://semiengineering.com/people/sang-s-wang/)
# [Sanjay Mittal](https://semiengineering.com/people/sanjay-mittal/)
# [Sanjay K Srivastava](https://semiengineering.com/people/sanjay-k-srivastava/)
# [Sarang Padalkar](https://semiengineering.com/people/sarang-padalkar/)
# [Satish Bagalkotkar](https://semiengineering.com/people/satish-bagalkotkar/)
# [Satish Padmanabhan](https://semiengineering.com/people/satish-padmanabhan/)
# [Satya Gupta](https://semiengineering.com/people/satya-gupta/)
# [Scott R. Powell](https://semiengineering.com/people/scott-r-powell/)
# [Scott T. Becker](https://semiengineering.com/people/scott-t-becker/)
# [Scott W. Houghton](https://semiengineering.com/people/scott-w-houghton/)
# [Sean Safarpour](https://semiengineering.com/people/sean-safarpour/)
# [Serge Maginot](https://semiengineering.com/people/serge-maginot/)
# [Seth Hallem](https://semiengineering.com/people/seth-hallem/)
# [Shahram Besharati](https://semiengineering.com/people/shahram-besharati/)
# [Shail Aditya](https://semiengineering.com/people/shail-aditya/)
# [Shajid Thiruvathodi](https://semiengineering.com/people/shajid-thiruvathodi/)
# [Shane Flint](https://semiengineering.com/people/shane-flint/)
# [Sharad Kapur](https://semiengineering.com/people/sharad-kapur/)
# [Shay Ben-Chorin](https://semiengineering.com/people/shay-ben-chorin/)
# [Shay Mizrachi](https://semiengineering.com/people/shay-mizrachi/)
# [Shen Lin](https://semiengineering.com/people/shen-lin/)
# [Sherif Eid](https://semiengineering.com/people/sherif-eid/)
# [Shiv Sikand](https://semiengineering.com/people/shiv-sikand/)
# [Shiv Tasker](https://semiengineering.com/people/shiv-tasker/)
# [Shubhodeep Roy Choudhury](https://semiengineering.com/people/shubhodeep-roy-choudhury/)
# [Simon Butler](https://semiengineering.com/people/simon-butler/)
# [Simon Davidmann](https://semiengineering.com/people/simon-davidmann/)
# [Simon Garrison](https://semiengineering.com/people/simon-garrison/)
# [Simon N. Springall](https://semiengineering.com/people/simon-n-springall/)
# [Snehanshu Shah](https://semiengineering.com/people/snehanshu-shah/)
# [Soo-Young Oh](https://semiengineering.com/people/soo-young-oh/)
# [Sotiris Bantast](https://semiengineering.com/people/sotiris-bantast/)
# [Srikanth Jadcherla](https://semiengineering.com/people/srikanth-jadcherla/)
# [Srinath Anantharaman](https://semiengineering.com/people/srinath-anantharaman/)
# [Srinivasan Durai](https://semiengineering.com/people/srinivasan-durai/)
# [Stanislav Ruev](https://semiengineering.com/people/stanislav-ruev/)
# [Stanley M. Hyduke](https://semiengineering.com/people/stanley-m-hyduke/)
# [Stanley Osher](https://semiengineering.com/people/stanley-osher/)
# [Stanley Yang](https://semiengineering.com/people/stanley-yang/)
# [Stefan Birman](https://semiengineering.com/people/stefan-birman/)
# [Stephane Hauradou](https://semiengineering.com/people/stephane-hauradou/)
# [StĂŠphane Leclercq](https://semiengineering.com/people/staphane-leclercq/)
# [Stephen Crosher](https://semiengineering.com/people/stephen-crosher/)
# [Stephen Fairbanks](https://semiengineering.com/people/stephen-fairbanks/)
# [Stephen J. Mellor](https://semiengineering.com/people/stephen-j-mellor/)
# [Steve Teig](https://semiengineering.com/people/steve-teig/)
# [Steve Bangert](https://semiengineering.com/people/steve-bangert/)
# [Steve Barlow](https://semiengineering.com/people/steve-barlow/)
# [Steve Carlson](https://semiengineering.com/people/steve-carlson/)
# [Steve Sapiro](https://semiengineering.com/people/steve-sapiro/)
# [Steve Walsh](https://semiengineering.com/people/steve-walsh/)
# [Steve White](https://semiengineering.com/people/steve-white/)
# [Steve Wilcox](https://semiengineering.com/people/steve-wilcox/)
# [Steve Yang](https://semiengineering.com/people/steve-yang/)
# [Steven Heinz](https://semiengineering.com/people/steven-heinz/)
# [Steven LâHer](https://semiengineering.com/people/steven-laeher/)
# [Steven Wang](https://semiengineering.com/people/steven-wang/)
# [Sudhir Kadkade](https://semiengineering.com/people/sudhir-kadkade/)
# [Sue Kunz](https://semiengineering.com/people/sue-kunz/)
# [Sujoy Chakravarty](https://semiengineering.com/people/sujoy-chakravarty/)
# [Sundar Iyer](https://semiengineering.com/people/sundar-iyer/)
# [Sundari Mitra](https://semiengineering.com/people/sundari-mitra/)
# [Sunil Jain](https://semiengineering.com/people/sunil-jain/)
# [Sunil Samel](https://semiengineering.com/people/sunil-samel/)
# [Sunil Talwar](https://semiengineering.com/people/sunil-talwar/)
# [Sycon Zohar](https://semiengineering.com/people/sycon-zohar/)
# [Sydney Lovely](https://semiengineering.com/people/sydney-lovely/)
# [Sylvian Kaiser](https://semiengineering.com/people/sylvian-kaiser/)
# [Tabor Smith](https://semiengineering.com/people/tabor-smith/)
# [Tae Hoon Song](https://semiengineering.com/people/tae-hoon-song/)
# [Tak Shigihara](https://semiengineering.com/people/tak-shigihara/)
# [Takis Breyiannis](https://semiengineering.com/people/takis-breyiannis/)
# [Tallis Blalack](https://semiengineering.com/people/tallis-blalack/)
# [Tapan Joshi](https://semiengineering.com/people/tapan-joshi/)
# [Tarak Parikh](https://semiengineering.com/people/tarak-parikh/)
# [Taylor Scanlon](https://semiengineering.com/people/taylor-scanlon/)
# [Terry Brewer](https://semiengineering.com/people/terry-brewer/)
# [Thomas Kailath](https://semiengineering.com/people/thomas-kailath/)
# [Thomas Niermann](https://semiengineering.com/people/thomas-niermann/)
# [Thomas Schultz](https://semiengineering.com/people/thomas-schultz/)
# [Tim Haynes](https://semiengineering.com/people/tim-haynes/)
# [Tobias Bjerregaard](https://semiengineering.com/people/tobias-bjerregaard/)
# [Todd Masey](https://semiengineering.com/people/todd-masey/)
# [Tom Paddock](https://semiengineering.com/people/tom-paddock/)
# [Tom Bruggere](https://semiengineering.com/people/tom-bruggere/)
# [Tom Cesear](https://semiengineering.com/people/tom-cesear/)
# [Tom Harris](https://semiengineering.com/people/tom-harris/)
# [Tom McWilliams](https://semiengineering.com/people/tom-mcwilliams/)
# [Tom Quarles](https://semiengineering.com/people/tom-quarles/)
# [Tony Curzon-Price](https://semiengineering.com/people/tony-curzon-price/)
# [Toshio Nakama](https://semiengineering.com/people/toshio-nakama/)
# [Trent McClements](https://semiengineering.com/people/trent-mcclements/)
# [Trent McConaghy](https://semiengineering.com/people/trent-mcconaghy/)
# [Uma Bondada](https://semiengineering.com/people/uma-bondada/)
# [Uri Tal](https://semiengineering.com/people/uri-tal/)
# [Vahagn Poghosyan](https://semiengineering.com/people/vahagn-poghosyan/)
# [Vaughn Betz](https://semiengineering.com/people/vaughn-betz/)
# [Venkat Iyer](https://semiengineering.com/people/venkat-iyer/)
# [Venugopal Kolathur](https://semiengineering.com/people/venugopal-kolathur/)
# [Victor Savenko](https://semiengineering.com/people/victor-savenko/)
# [Vigyan Singhal](https://semiengineering.com/people/vigyan-singhal/)
# [Vikram Jandhyala](https://semiengineering.com/people/vikram-jandhyala/)
# [Vincent Perrier](https://semiengineering.com/people/vincent-perrier/)
# [Vincent Thibaut](https://semiengineering.com/people/vincent-thibaut/)
# [Vinod K. Agarwal](https://semiengineering.com/people/vinod-k-agarwal/)
# [Vinod Kathail](https://semiengineering.com/people/vinod-kathail/)
# [Vinod Narayanan](https://semiengineering.com/people/vinod-narayanan/)
# [Virantha N. Ekanayake](https://semiengineering.com/people/virantha-n-ekanayake/)
# [Vishal Moondhra](https://semiengineering.com/people/vishal-moondhra/)
# [Vivek Raghavan](https://semiengineering.com/people/vivek-raghavan/)
# [Vivek Bhat](https://semiengineering.com/people/vivek-bhat/)
# [Vivek Pawar](https://semiengineering.com/people/vivek-pawar/)
# [Vlad Potanin](https://semiengineering.com/people/vlad-potanin/)
# [Vladimir Schellbach](https://semiengineering.com/people/vladimir-schellbach/)
# [Vojin Zivojnovic](https://semiengineering.com/people/vojin-zivojnovic/)
# [Wai Yan (William) Ho](https://semiengineering.com/people/wai-yan-william-ho/)
# [Walden (Wally) Rhines](https://semiengineering.com/people/walden-rhines/)
# [Wally Haas](https://semiengineering.com/people/wally-haas/)
# [Walter Chan](https://semiengineering.com/people/walter-chan/)
# [Walter Daems](https://semiengineering.com/people/walter-daems/)
# [Warren Savage](https://semiengineering.com/people/warren-savage/)
# [Wayne Dai](https://semiengineering.com/people/wayne-dai/)
# [Wayne Marking](https://semiengineering.com/people/wayne-marking/)
# [Weihua Sheng](https://semiengineering.com/people/weihua-sheng/)
# [Weiping (Peter) Shi](https://semiengineering.com/people/weiping-peter-shi/)
# [Weize Xie](https://semiengineering.com/people/weize-xie/)
# [Werner Geurts](https://semiengineering.com/people/werner-geurts/)
# [Will Herman](https://semiengineering.com/people/will-herman/)
# [Willem vanCleemput](https://semiengineering.com/people/willem-vancleemput/)
# [Willi Brandenburg](https://semiengineering.com/people/willi-brandenburg/)
# [William âBillâ Billowitch](https://semiengineering.com/people/william-aeoebillae%C2%9D-billowitch/)
# [Wim Schoenmaker](https://semiengineering.com/people/wim-schoenmaker/)
# [Wim Verhaegen](https://semiengineering.com/people/wim-verhaegen/)
# [Wlodek Kurjanowicz](https://semiengineering.com/people/wlodek-kurjanowicz/)
# [Wojciech Sakowski](https://semiengineering.com/people/wojciech-sakowski/)
# [Wolfram BĂźttner](https://semiengineering.com/people/wolfram-ba%C2%BCttner/)
# [Wu-Tung Cheng](https://semiengineering.com/people/wu-tung-cheng/)
# [WĹodzimierz Wrona](https://semiengineering.com/people/waodzimierz-wrona/)
# [Xerxes Wania](https://semiengineering.com/people/xerxes-wania/)
# [Xisheng Zhang](https://semiengineering.com/people/xisheng-zhang/)
# [Xuequn (Kevin) Xiang](https://semiengineering.com/people/xuequn-kevin-xiang/)
# [Yao-Ting Wang](https://semiengineering.com/people/yao-ting-wang/)
# [Yi (Bob) Xu](https://semiengineering.com/people/yi-bob-xu/)
# [Yoav Hollander](https://semiengineering.com/people/yoav-hollander/)
# [Yorgos Koutsoyannopoulost](https://semiengineering.com/people/yorgos-koutsoyannopoulost/)
# [Youn-Long (Steve) Lin](https://semiengineering.com/people/youn-long-steve-lin/)
# [Yuan Lu](https://semiengineering.com/people/yuan-lu/)
# [Yunshan Zhu](https://semiengineering.com/people/yunshan-zhu/)
# [Yuri Feinberg](https://semiengineering.com/people/yuri-feinberg/)
# [Z.M Simon Li](https://semiengineering.com/people/z-m-simon-li/)
# [Zhihong Liu](https://semiengineering.com/people/zhihong-liu/)
# [Zhonghai Lu](https://semiengineering.com/people/zhonghai-lu/)
# [Zied Marrakchi](https://semiengineering.com/people/zied-marrakchi/)
# [Zvi Or-Bach](https://semiengineering.com/people/zvi-or-bach/)
# [0-In Design Automation Inc.](https://semiengineering.com/entities/0-in-design-automation-inc/)
# [3Soft Corporation](https://semiengineering.com/entities/3soft-corporation/)
# [@HDL](https://semiengineering.com/entities/hdl/)
# [Aachen University of Technology](https://semiengineering.com/entities/aachen-university-of-technology/)
# [ACAD Corp](https://semiengineering.com/entities/acad-corp/)
# [Accel Technologies Inc.](https://semiengineering.com/entities/accel-technologies-inc/)
# [Accelerant Networks, Inc.](https://semiengineering.com/entities/accelerant-networks-inc/)
# [Accelerated Technology (UK) Ltd.](https://semiengineering.com/entities/accelerated-technology-uk-ltd/)
# [Accelerated Technology Inc.](https://semiengineering.com/entities/accelerated-technology-inc/)
# [Accelicon Technologies](https://semiengineering.com/entities/accelicon-technologies/)
# [Accellera](https://semiengineering.com/entities/accellera/)
# [Accellera Systems Initiative](https://semiengineering.com/entities/accellera-systems-initiative/)
# [Accellera UCIS WG](https://semiengineering.com/entities/accellera-ucis-wg/)
# [Accent S.R.L](https://semiengineering.com/entities/accent-s-r-l/)
# [Accolade Design Automation](https://semiengineering.com/entities/accolade-design-automation/)
# [ACEO Technology](https://semiengineering.com/entities/aceo-technology/)
# [Achronix Semiconductor Corporation](https://semiengineering.com/entities/achronix-semiconductor-corporation/)
# [Acorn Computer Group](https://semiengineering.com/entities/acorn-computer-group/)
# [Actel Corp.](https://semiengineering.com/entities/actel-corp/)
# [Adapt IP](https://semiengineering.com/entities/adapt-ip/)
# [ADAS Software](https://semiengineering.com/entities/adas-software/)
# [Adelante Technology](https://semiengineering.com/entities/adelante-technology/)
# [Adesto Technologies Corp.](https://semiengineering.com/entities/adesto-technologies-corp/)
# [Adicsys](https://semiengineering.com/entities/adicsys/)
# [Advanced CAM Technologies, Inc.](https://semiengineering.com/entities/advanced-cam-technologies-inc/)
# [Advanced Micro Devices (AMD)](https://semiengineering.com/entities/advanced-micro-devices-amd/)
# [Advanced Microelectronics](https://semiengineering.com/entities/advanced-microelectronics/)
# [Advanced RISC Machines Ltd.](https://semiengineering.com/entities/advanced-risc-machines-ltd/)
# [Advanced Technology Center](https://semiengineering.com/entities/advanced-technology-center/)
# [Advanced Test Technology, Inc.](https://semiengineering.com/entities/advanced-test-technology-inc/)
# [Advantest Corporation](https://semiengineering.com/entities/advantest-corporation/)
# [AGGIOS, Inc.](https://semiengineering.com/entities/aggios-inc/)
# [Agilent EEsof EDA](https://semiengineering.com/entities/agilent-eesof-eda/)
# [Agilent Technologies](https://semiengineering.com/entities/agilent-technologies/)
# [Agility Design Solutions](https://semiengineering.com/entities/agility-design-solutions/)
# [Agnisys, Inc.](https://semiengineering.com/entities/agnisys-inc/)
# [Alarity Corporation](https://semiengineering.com/entities/alarity-corporation/)
# [Alchemy Semiconductor](https://semiengineering.com/entities/alchemy-semiconductor/)
# [Aldec, Inc.](https://semiengineering.com/entities/aldec-inc/)
# [Algotochip Corporation](https://semiengineering.com/entities/algotochip-corporation/)
# [Allant Software](https://semiengineering.com/entities/allant-software/)
# [Allegro DVT](https://semiengineering.com/entities/allegro-dvt/)
# [Alphabit](https://semiengineering.com/entities/alphabit/)
# [Alphawave Semi](https://semiengineering.com/entities/alphawave-semi/)
# [Alta Group of Cadence](https://semiengineering.com/entities/alta-group-of-cadence/)
# [Altera Corporation](https://semiengineering.com/entities/altera-corporation/)
# [Altium, Inc.](https://semiengineering.com/entities/altium-inc/)
# [Altius Solutions Inc.](https://semiengineering.com/entities/altius-solutions-inc/)
# [Altos Design Automation, Inc.](https://semiengineering.com/entities/altos-design-automation-inc/)
# [Ambit Design Systems, Inc.](https://semiengineering.com/entities/ambit-design-systems-inc/)
# [AMIQ EDA](https://semiengineering.com/entities/amiq-eda/)
# [Amkor Technology](https://semiengineering.com/entities/amkor-technology/)
# [AMS AG](https://semiengineering.com/entities/ams-ag/)
# [Anacad Electrical Engineering Software GmbH](https://semiengineering.com/entities/anacad-electrical-engineering-software-gmbh/)
# [Anagram Inc.](https://semiengineering.com/entities/anagram-inc/)
# [Analog Bits Inc.](https://semiengineering.com/entities/analog-bits-inc/)
# [Analog Design Automation, Inc.](https://semiengineering.com/entities/analog-design-automation-inc/)
# [Analog Design Tools Inc.](https://semiengineering.com/entities/analog-design-tools-inc/)
# [Analogy Inc.](https://semiengineering.com/entities/analogy-inc/)
# [Anasim](https://semiengineering.com/entities/anasim/)
# [Andes Technology](https://semiengineering.com/entities/andes-technology/)
# [Andes Technology Corp.](https://semiengineering.com/entities/andes-technology-corp/)
# [Ansys](https://semiengineering.com/entities/ansys/)
# [Antares](https://semiengineering.com/entities/antares/)
# [Antrim Design Systems Inc.](https://semiengineering.com/entities/antrim-design-systems-inc/)
# [Apache Design Solutions, Inc.](https://semiengineering.com/entities/apache-design-solutions-inc/)
# [Apical Ltd.](https://semiengineering.com/entities/apical-ltd/)
# [APLAC Solutions Corp.](https://semiengineering.com/entities/aplac-solutions-corp/)
# [Aplus Design Technologies Inc.](https://semiengineering.com/entities/aplus-design-technologies-inc/)
# [Applied Materials, Inc.](https://semiengineering.com/entities/applied-materials-inc/)
# [Applied Simulation Technology](https://semiengineering.com/entities/applied-simulation-technology/)
# [Applied Wave Research, Inc.](https://semiengineering.com/entities/applied-wave-research-inc/)
# [Apres Technologies](https://semiengineering.com/entities/apres-technologies/)
# [Apteq Design Systems Inc.](https://semiengineering.com/entities/apteq-design-systems-inc/)
# [Aptix Corporation](https://semiengineering.com/entities/aptix-corporation/)
# [Arasan Chip Systems](https://semiengineering.com/entities/arasan-chip-systems/)
# [ARC International PLC](https://semiengineering.com/entities/arc-international-plc/)
# [Arcad SA](https://semiengineering.com/entities/arcad-sa/)
# [Arcadia Innovation, Inc.](https://semiengineering.com/entities/arcadia-innovation-inc/)
# [Archer Systems](https://semiengineering.com/entities/archer-systems/)
# [ArchPro Design Automation, Inc.](https://semiengineering.com/entities/archpro-design-automation-inc/)
# [ArcSys Inc.](https://semiengineering.com/entities/arcsys-inc/)
# [Arexsys S.A.](https://semiengineering.com/entities/arexsys-s-a/)
# [Argon Design Ltd.](https://semiengineering.com/entities/argon-design-ltd/)
# [Aristo Technology, Inc.](https://semiengineering.com/entities/aristo-technology-inc/)
# [Arithmatica](https://semiengineering.com/entities/arithmatica/)
# [Arium](https://semiengineering.com/entities/arium/)
# [Arkos Design Systems](https://semiengineering.com/entities/arkos-design-systems/)
# [Arkos Emulation Unit](https://semiengineering.com/entities/arkos-emulation-unit/)
# [Arm](https://semiengineering.com/entities/arm/)
# [Arrow Devices Pvt. Ltd.](https://semiengineering.com/entities/arrow-devices-pvt-ltd/)
# [ARS Microsystems Ltd.](https://semiengineering.com/entities/ars-microsystems-ltd/)
# [Arteris](https://semiengineering.com/entities/arterisip/)
# [Artisan Components, Inc.](https://semiengineering.com/entities/artisan-components-inc/)
# [ASE (Advanced Semiconductor Engineering)](https://semiengineering.com/entities/ase/)
# [ASML](https://semiengineering.com/entities/asml/)
# [Aspec Technology Inc](https://semiengineering.com/entities/aspec-technology-inc/)
# [ASSET InterTech](https://semiengineering.com/entities/asset-intertech/)
# [ASTC](https://semiengineering.com/entities/astc/)
# [Astronics Test Systems](https://semiengineering.com/entities/astronics-test-systems/)
# [Asygn](https://semiengineering.com/entities/asygn/)
# [Atair GmbH](https://semiengineering.com/entities/atair-gmbh/)
# [AtaiTec Corp.](https://semiengineering.com/entities/ataitec-corp/)
# [ATEEDA Ltd.](https://semiengineering.com/entities/ateeda-ltd/)
# [Atlantic Aerospace Electronics Corp.](https://semiengineering.com/entities/atlantic-aerospace-electronics-corp/)
# [ATopTech](https://semiengineering.com/entities/atoptech/)
# [Atrenta, Inc.](https://semiengineering.com/entities/atrenta-inc/)
# [Ausdia, Inc.](https://semiengineering.com/entities/ausdia-inc/)
# [AutoESL Design Technologies, Inc.](https://semiengineering.com/entities/autoesl-design-technologies-inc/)
# [Automated Integrated Design Systems](https://semiengineering.com/entities/automated-integrated-design-systems/)
# [Automated Systems, Inc.](https://semiengineering.com/entities/automated-systems-inc/)
# [Automatic Parallel Designs](https://semiengineering.com/entities/automatic-parallel-designs/)
# [Automotive Electronics Council (AEC)](https://semiengineering.com/entities/automotive-electronics-council-aec/)
# [Avalon Microelectronics Inc.](https://semiengineering.com/entities/avalon-microelectronics-inc/)
# [Avant! Corporation](https://semiengineering.com/entities/avant-corporation/)
# [Averant, Inc.](https://semiengineering.com/entities/averant-inc/)
# [AverStar](https://semiengineering.com/entities/averstar/)
# [Avery Design Systems](https://semiengineering.com/entities/avery-design-systems/)
# [Award Software](https://semiengineering.com/entities/award-software/)
# [Axiom Daterer Skandinavien AB](https://semiengineering.com/entities/axiom-daterer-skandinavien-ab/)
# [Axiom Design Automation](https://semiengineering.com/entities/axiom-design-automation/)
# [Axiomise](https://semiengineering.com/entities/axiomise/)
# [Axis Systems, Inc.](https://semiengineering.com/entities/axis-systems-inc/)
# [AXYS Design Automation, Inc.](https://semiengineering.com/entities/axys-design-automation-inc/)
# [Azuro, Inc.](https://semiengineering.com/entities/azuro-inc/)
# [A\|RT Technology of Adelante](https://semiengineering.com/entities/art-technology-of-adelante/)
# [Baya Systems](https://semiengineering.com/entities/baya-systems/)
# [BDTI](https://semiengineering.com/entities/bdti/)
# [Beach Solutions](https://semiengineering.com/entities/beach-solutions/)
# [Bell Labs DA group of Lucent](https://semiengineering.com/entities/bell-labs-da-group-of-lucent/)
# [Benelux B.V](https://semiengineering.com/entities/benelux-b-v/)
# [Berkeley Design Automation, Inc.](https://semiengineering.com/entities/berkeley-design-automation-inc/)
# [BlazeDFM](https://semiengineering.com/entities/blazedfm/)
# [Blue Cheetah](https://semiengineering.com/entities/blue-cheetah/)
# [Blue Pearl Software, Inc.](https://semiengineering.com/entities/blue-pearl-software-inc/)
# [Bluespec, Inc.](https://semiengineering.com/entities/bluespec-inc/)
# [BOPS, Inc.](https://semiengineering.com/entities/bops-inc/)
# [Boulder Creek Engineering](https://semiengineering.com/entities/boulder-creek-engineering/)
# [Brandenburg GmbH](https://semiengineering.com/entities/brandenburg-gmbh/)
# [Breker Verification Systems](https://semiengineering.com/entities/breker-verification-systems/)
# [Brewer Science](https://semiengineering.com/entities/brewer-science/)
# [Bridges2Silicon, Inc.](https://semiengineering.com/entities/bridges2silicon-inc/)
# [Brite Semiconductor](https://semiengineering.com/entities/brite-semiconductor/)
# [Broadcom](https://semiengineering.com/entities/broadcom/)
# [Bruker](https://semiengineering.com/entities/bruker/)
# [BTA Technology](https://semiengineering.com/entities/bta-technology/)
# [BTA Ultima Inc.](https://semiengineering.com/entities/bta-ultima-inc/)
# [C Level Design, Inc.](https://semiengineering.com/entities/c-level-design-inc/)
# [C2 Design Automation](https://semiengineering.com/entities/c2-design-automation/)
# [CAD Framework Initiative](https://semiengineering.com/entities/cad-framework-initiative/)
# [Cadabra Design Automation, Inc.](https://semiengineering.com/entities/cadabra-design-automation-inc/)
# [Cadence 802.11 wireless LAN IP](https://semiengineering.com/entities/cadence-802-11-wireless-lan-ip/)
# [Cadence Design Foundry](https://semiengineering.com/entities/cadence-design-foundry/)
# [Cadence Design Systems](https://semiengineering.com/entities/cadence-design-systems/)
# [Cadence PANTA IP cores](https://semiengineering.com/entities/cadence-panta-ip-cores/)
# [Cadis GmbH](https://semiengineering.com/entities/cadis-gmbh/)
# [CADIX Corporation](https://semiengineering.com/entities/cadix-corporation/)
# [CADIX ECAD division](https://semiengineering.com/entities/cadix-ecad-division/)
# [CadMOS Design Technology, Inc.](https://semiengineering.com/entities/cadmos-design-technology-inc/)
# [Cadnetix Corporation](https://semiengineering.com/entities/cadnetix-corporation/)
# [CAE systems](https://semiengineering.com/entities/cae-systems/)
# [CAE Technology Inc.](https://semiengineering.com/entities/cae-technology-inc/)
# [Caeco Inc.](https://semiengineering.com/entities/caeco-inc/)
# [Caedent Corporation](https://semiengineering.com/entities/caedent-corporation/)
# [Caetek Inc.](https://semiengineering.com/entities/caetek-inc/)
# [California Design Automation, Inc.](https://semiengineering.com/entities/california-design-automation-inc/)
# [Calma Company](https://semiengineering.com/entities/calma-company/)
# [Calypto Design Systems, Inc.](https://semiengineering.com/entities/calypto-design-systems-inc/)
# [Carbon Design Systems](https://semiengineering.com/entities/carbon-design-systems/)
# [CARDtools Systems](https://semiengineering.com/entities/cardtools-systems/)
# [Carnegie Mellon University](https://semiengineering.com/entities/carnegie-mellon-university/)
# [Cascade Semiconductor Solutions, Inc.](https://semiengineering.com/entities/cascade-semiconductor-solutions-inc/)
# [CAST, Inc.](https://semiengineering.com/entities/cast-inc/)
# [Catalytic Inc.](https://semiengineering.com/entities/catalytic-inc/)
# [Catapult C Product Division](https://semiengineering.com/entities/catapult-c-product-division/)
# [CEA](https://semiengineering.com/entities/cea/)
# [CEA-Leti](https://semiengineering.com/entities/cea-leti/)
# [Celestry Design Technologies Inc.](https://semiengineering.com/entities/celestry-design-technologies-inc/)
# [Celoxica Holding Plc.](https://semiengineering.com/entities/celoxica-holding-plc/)
# [Certess Inc.](https://semiengineering.com/entities/certess-inc/)
# [Certus Semiconductor](https://semiengineering.com/entities/certus-semiconductor/)
# [CEVA](https://semiengineering.com/entities/ceva/)
# [CheckLogic Systems inc.](https://semiengineering.com/entities/checklogic-systems-inc/)
# [Chip & Chip, Inc.](https://semiengineering.com/entities/chip-chip-inc/)
# [Chip Estimate Corp](https://semiengineering.com/entities/chip-estimate-corp/)
# [Chip Path Design Systems](https://semiengineering.com/entities/chip-path-design-systems/)
# [ChipAgents](https://semiengineering.com/entities/alpha-design-ai-chipagents/)
# [CHIPit business unit](https://semiengineering.com/entities/chipit-business-unit/)
# [ChipStart LLC](https://semiengineering.com/entities/chipstart-llc/)
# [Chronologic Simulation](https://semiengineering.com/entities/chronologic-simulation/)
# [Chronology Inc.](https://semiengineering.com/entities/chronology-inc/)
# [Chrysalis Symbolic Design, Inc.](https://semiengineering.com/entities/chrysalis-symbolic-design-inc/)
# [CIDA Technology, Inc.](https://semiengineering.com/entities/cida-technology-inc/)
# [CIM-Team GmbH](https://semiengineering.com/entities/cim-team-gmbh/)
# [CiraNova Inc.](https://semiengineering.com/entities/ciranova-inc/)
# [Clear Shape Technologies](https://semiengineering.com/entities/clear-shape-technologies/)
# [Cliosoft, Inc.](https://semiengineering.com/entities/cliosoft-inc/)
# [CLK Computer-Aided Design, Inc.](https://semiengineering.com/entities/clk-computer-aided-design-inc/)
# [CLK Design Automation, Inc.](https://semiengineering.com/entities/clk-design-automation-inc/)
# [Co-Design Automation, Inc.](https://semiengineering.com/entities/co-design-automation-inc/)
# [Codasip Ltd.](https://semiengineering.com/entities/codasip-ltd/)
# [Codefast, Inc](https://semiengineering.com/entities/codefast-inc/)
# [Codenomicon Oy](https://semiengineering.com/entities/codenomicon-oy/)
# [CodeSourcery Inc.](https://semiengineering.com/entities/codesourcery-inc/)
# [CoFluent Design](https://semiengineering.com/entities/cofluent-design/)
# [Cohu Inc.](https://semiengineering.com/entities/cohu/)
# [Comdisco Systems Inc.](https://semiengineering.com/entities/comdisco-systems-inc/)
# [ComLSI](https://semiengineering.com/entities/comlsi/)
# [Compact Model Coalition](https://semiengineering.com/entities/compact-model-council/)
# [Compass Design Automation](https://semiengineering.com/entities/compass-design-automation/)
# [Compiled Designs GmbH](https://semiengineering.com/entities/compiled-designs-gmbh/)
# [Computer Simulation Technology GmbH](https://semiengineering.com/entities/computer-simulation-technology-gmbh/)
# [Computervision, Inc.](https://semiengineering.com/entities/computervision-inc/)
# [Computing-Tabulating-Recording Company](https://semiengineering.com/entities/computing-tabulating-recording-company/)
# [Concept Engineering GmbH](https://semiengineering.com/entities/concept-engineering-gmbh/)
# [Context Corporation](https://semiengineering.com/entities/context-corporation/)
# [Contour Design Systems, Inc.](https://semiengineering.com/entities/contour-design-systems-inc/)
# [Conversant Intellectual Property Management](https://semiengineering.com/entities/conversant-intellectual-property-management/)
# [Cooper and Chyan Technology Inc.](https://semiengineering.com/entities/cooper-and-chyan-technology-inc/)
# [Cortus S.A.S.](https://semiengineering.com/entities/cortus-s-a-s/)
# [Cosmic Circuits](https://semiengineering.com/entities/cosmic-circuits/)
# [CoSoft Ltd.](https://semiengineering.com/entities/cosoft-ltd/)
# [Council of EDA Standards Committee](https://semiengineering.com/entities/council-of-eda-standards-committee/)
# [Coventor, a Lam Research Company](https://semiengineering.com/entities/coventor-inc/)
# [CoverMeter Tool](https://semiengineering.com/entities/covermeter-tool/)
# [CoWare LLC](https://semiengineering.com/entities/coware-llc/)
# [Coyote Systems](https://semiengineering.com/entities/coyote-systems/)
# [Cre8 Ventures](https://semiengineering.com/entities/cre8-ventures/)
# [Credence Systems Corporation](https://semiengineering.com/entities/credence-systems-corporation/)
# [Critical Blue](https://semiengineering.com/entities/critical-blue/)
# [Crosslight Software, Inc.](https://semiengineering.com/entities/crosslight-software-inc/)
# [CyberOptics, a Nordson Test & Inspection company](https://semiengineering.com/entities/cyberoptics/)
# [CycleC and other technology assets](https://semiengineering.com/entities/cyclec-and-other-technology-assets/)
# [Cycuity](https://semiengineering.com/entities/tortuga-logic/)
# [Cynapps](https://semiengineering.com/entities/cynapps/)
# [D2S](https://semiengineering.com/entities/d2s/)
# [Daisy Systems Corporation](https://semiengineering.com/entities/daisy-systems-corporation/)
# [Dassault Systèmes](https://semiengineering.com/entities/dassault-systa%C2%A8mes/)
# [Dasys](https://semiengineering.com/entities/dasys/)
# [Data I/O](https://semiengineering.com/entities/data-io/)
# [Datalink Far East, Ltd](https://semiengineering.com/entities/datalink-far-east-ltd/)
# [Dazix](https://semiengineering.com/entities/dazix/)
# [DDE-EDA A/S](https://semiengineering.com/entities/dde-eda-as/)
# [Deerbrook Systems Inc.](https://semiengineering.com/entities/deerbrook-systems-inc/)
# [Defacto Technologies](https://semiengineering.com/entities/defacto-technologies/)
# [Defense Advanced Research Agency (DARPA)](https://semiengineering.com/entities/defense-advanced-research-agency-darpa/)
# [DelSoft India Pvt. Ltd](https://semiengineering.com/entities/delsoft-india-pvt-ltd/)
# [DELTA Microelectronics](https://semiengineering.com/entities/delta-microelectronics/)
# [Denali Software, Inc.](https://semiengineering.com/entities/denali-software-inc/)
# [Desantage Corporation](https://semiengineering.com/entities/desantage-corporation/)
# [Descartes Automation Systems](https://semiengineering.com/entities/descartes-automation-systems/)
# [Descon InformationsSysteme GmbH](https://semiengineering.com/entities/descon-informationssysteme-gmbh/)
# [Design Acceleration Inc.](https://semiengineering.com/entities/design-acceleration-inc/)
# [DesignAdvance Systems Inc.](https://semiengineering.com/entities/designadvance-systems-inc/)
# [DesignPRO Inc.](https://semiengineering.com/entities/designpro-inc/)
# [DĂŠtente Technology, Inc.](https://semiengineering.com/entities/datente-technology-inc/)
# [Diablo Research Co. LLC](https://semiengineering.com/entities/diablo-research-co-llc/)
# [Digital Blocks](https://semiengineering.com/entities/digital-blocks/)
# [Dini Group](https://semiengineering.com/entities/dini-group/)
# [Docea Power](https://semiengineering.com/entities/docea-power/)
# [Dolphin Integration](https://semiengineering.com/entities/dolphin-integration/)
# [Dorado Design Automation, Inc.](https://semiengineering.com/entities/dorado-design-automation-inc/)
# [Doulos](https://semiengineering.com/entities/doulos/)
# [dQdt, Inc.](https://semiengineering.com/entities/dqdt-inc/)
# [DR YIELD](https://semiengineering.com/entities/dr-yield/)
# [DRC:DA](https://semiengineering.com/entities/drcda/)
# [DSM Technologies Inc.](https://semiengineering.com/entities/dsm-technologies-inc/)
# [DSP Division of Philips Semiconductor](https://semiengineering.com/entities/dsp-division-of-philips-semiconductor/)
# [Duolog Technologies Ltd.](https://semiengineering.com/entities/duolog-technologies-ltd/)
# [DXCorr Design, Inc.](https://semiengineering.com/entities/dxcorr-design-inc/)
# [Dynamic Soft analysis Inc.](https://semiengineering.com/entities/dynamic-soft-analysis-inc/)
# [E-Z-CAD, Inc.](https://semiengineering.com/entities/e-z-cad-inc/)
# [Eagle Design Automation](https://semiengineering.com/entities/eagle-design-automation/)
# [Eagleware, Inc.](https://semiengineering.com/entities/eagleware-inc/)
# [Eagleware-Elanix](https://semiengineering.com/entities/eagleware-elanix/)
# [eASIC Corporation](https://semiengineering.com/entities/easic-corporation/)
# [eBeam Initiative](https://semiengineering.com/entities/ebeam-initiative/)
# [eBizAutomation Inc.](https://semiengineering.com/entities/ebizautomation-inc/)
# [ECAD Inc.](https://semiengineering.com/entities/ecad-inc/)
# [Ăcole Polytechnique de MontrĂŠal](https://semiengineering.com/entities/a%E2%80%B0cole-polytechnique-de-montraal/)
# [ECSI](https://semiengineering.com/entities/ecsi/)
# [EDA Systems](https://semiengineering.com/entities/eda-systems/)
# [EDAC](https://semiengineering.com/entities/edac/)
# [EdXact SA](https://semiengineering.com/entities/edxact-sa/)
# [EEsof, Inc.](https://semiengineering.com/entities/eesof-inc/)
# [efabless.com](https://semiengineering.com/entities/efabless-com/)
# [Elanix, Inc.](https://semiengineering.com/entities/elanix-inc/)
# [Electronic System Design Alliance](https://semiengineering.com/entities/electronic-system-design-alliance/)
# [Eliyan](https://semiengineering.com/entities/eliyan/)
# [Elliptic Technologies](https://semiengineering.com/entities/elliptic-technologies/)
# [Elsip AB](https://semiengineering.com/entities/elsip-ab/)
# [EMA Design Automation](https://semiengineering.com/entities/ema-design-automation/)
# [Embedded Alley Solutions](https://semiengineering.com/entities/embedded-alley-solutions/)
# [Embedded Performance Inc.](https://semiengineering.com/entities/embedded-performance-inc/)
# [Embedded Solutions Limited](https://semiengineering.com/entities/embedded-solutions-limited/)
# [Embedded Vision Alliance](https://semiengineering.com/entities/embedded-vision-alliance/)
# [Emulation and Verification Engineering](https://semiengineering.com/entities/emulation-and-verification-engineering/)
# [Emulation division of Mitsui Bussan](https://semiengineering.com/entities/emulation-division-of-mitsui-bussan/)
# [EnSilica Ltd.](https://semiengineering.com/entities/ensilica-ltd/)
# [Entasys Design Inc.](https://semiengineering.com/entities/entasys-design-inc/)
# [EPIC Design Technology, Inc.](https://semiengineering.com/entities/epic-design-technology-inc/)
# [Escalade Corp.](https://semiengineering.com/entities/escalade-corp/)
# [eSilicon Corporation](https://semiengineering.com/entities/esilicon-corporation/)
# [ESL assets of Agility](https://semiengineering.com/entities/esl-assets-of-agility/)
# [ESL assets of Celoxica](https://semiengineering.com/entities/esl-assets-of-celoxica/)
# [Esperan Ltd.](https://semiengineering.com/entities/esperan-ltd/)
# [eTop Design Automation](https://semiengineering.com/entities/etop-design-automation/)
# [EuroMIPS Systems](https://semiengineering.com/entities/euromips-systems/)
# [European Design Center](https://semiengineering.com/entities/european-design-center/)
# [European Microelectronics Academy](https://semiengineering.com/entities/european-microelectronics-academy/)
# [EV Group](https://semiengineering.com/entities/ev-group/)
# [Evans Analytical Group](https://semiengineering.com/entities/evans-analytical-group/)
# [Evatronix IP Design Business](https://semiengineering.com/entities/evatronix-ip-design-business/)
# [Evatronix SA](https://semiengineering.com/entities/evatronix-sa/)
# [EverCAD Corporation](https://semiengineering.com/entities/evercad-corporation/)
# [Everest Design Automation, Inc.](https://semiengineering.com/entities/everest-design-automation-inc/)
# [Excellent Design Inc.](https://semiengineering.com/entities/excellent-design-inc/)
# [Excellicon Inc.](https://semiengineering.com/entities/excellicon-inc/)
# [Exemplar Logic, Inc.](https://semiengineering.com/entities/exemplar-logic-inc/)
# [Eximius Design](https://semiengineering.com/entities/eximius-design/)
# [Expedera](https://semiengineering.com/entities/expedera/)
# [ExperTest](https://semiengineering.com/entities/expertest/)
# [ExpertIO, Inc.](https://semiengineering.com/entities/expertio-inc/)
# [Expressive Systems](https://semiengineering.com/entities/expressive-systems/)
# [Extreme DA, Corp.](https://semiengineering.com/entities/extreme-da-corp/)
# [Fairchild Semiconductor](https://semiengineering.com/entities/fairchild-semiconductor/)
# [Falanx Microsystems AS](https://semiengineering.com/entities/falanx-microsystems-as/)
# [FEI â Knights Technology](https://semiengineering.com/entities/fei-knights-technology/)
# [FEI Company](https://semiengineering.com/entities/fei-company/)
# [Fenix Design Automation](https://semiengineering.com/entities/fenix-design-automation/)
# [Ferric Semiconductor Inc.](https://semiengineering.com/entities/ferric-semiconductor-inc/)
# [Fidus Systems Inc.](https://semiengineering.com/entities/fidus-systems-inc/)
# [First Earth Ltd.](https://semiengineering.com/entities/first-earth-ltd/)
# [FishTail Design Automation, Inc.](https://semiengineering.com/entities/fishtail-design-automation-inc/)
# [Flex Logix Technologies, Inc.](https://semiengineering.com/entities/flex-logix-technologies-inc/)
# [Flexras Technologies SAS](https://semiengineering.com/entities/flexras-technologies-sas/)
# [Flomerics EM software](https://semiengineering.com/entities/flomerics-em-software/)
# [Flomerics Group PLC](https://semiengineering.com/entities/flomerics-group-plc/)
# [Flometrics group Plc](https://semiengineering.com/entities/flometrics-group-plc/)
# [Flowmaster Ltd.](https://semiengineering.com/entities/flowmaster-ltd/)
# [FormFactor](https://semiengineering.com/entities/formfactor/)
# [Forte Design Systems](https://semiengineering.com/entities/forte-design-systems/)
# [FPGA technology of Kilopass](https://semiengineering.com/entities/fpga-technology-of-kilopass/)
# [Fractal Technologies](https://semiengineering.com/entities/fractal-technologies/)
# [Fraunhofer IIS EAS](https://semiengineering.com/entities/fraunhofer-iis-eas/)
# [Freescale â Virtual Garage](https://semiengineering.com/entities/freescale-virtual-garage/)
# [Freescale Semiconductor](https://semiengineering.com/entities/freescale-semiconductor/)
# [Frequency Technology](https://semiengineering.com/entities/frequency-technology/)
# [Frontier Design](https://semiengineering.com/entities/frontier-design/)
# [Frontline Design Automation, Inc.](https://semiengineering.com/entities/frontline-design-automation-inc/)
# [G-Analog Design Automation Ltd.](https://semiengineering.com/entities/g-analog-design-automation-ltd/)
# [Galaxy Semiconductor](https://semiengineering.com/entities/galaxy-semiconductor/)
# [Gambit Automated Design, Inc.](https://semiengineering.com/entities/gambit-automated-design-inc/)
# [Gatefield](https://semiengineering.com/entities/gatefield/)
# [GateRocket](https://semiengineering.com/entities/gaterocket/)
# [Gateway Design Automation](https://semiengineering.com/entities/gateway-design-automation/)
# [Gear Design Solutions, Inc.](https://semiengineering.com/entities/gear-design-solutions-inc/)
# [Gemini Design Technology Inc.](https://semiengineering.com/entities/gemini-design-technology-inc/)
# [Genedax](https://semiengineering.com/entities/genedax/)
# [Georgia Tech](https://semiengineering.com/entities/georgia-tech/)
# [Get2Chip Inc.](https://semiengineering.com/entities/get2chip-inc/)
# [Giga Scale Integration Corporation](https://semiengineering.com/entities/giga-scale-integration-corporation/)
# [Global Semiconductor Alliance](https://semiengineering.com/entities/global-semiconductor-alliance/)
# [Global Unichip Corp.](https://semiengineering.com/entities/global-unichip-corp/)
# [GlobalFoundries](https://semiengineering.com/entities/globalfoundries/)
# [Goanna Software Pty Ltd](https://semiengineering.com/entities/goanna-software-pty-ltd/)
# [Gold Standard Simulations Ltd.](https://semiengineering.com/entities/gold-standard-simulations-ltd/)
# [Gradient DAâs electrothermal analysis technology](https://semiengineering.com/entities/gradient-das-electrothermal-analysis-technology/)
# [Gradient Design Automation](https://semiengineering.com/entities/gradient-design-automation/)
# [Green Mountain Computing Systems](https://semiengineering.com/entities/green-mountain-computing-systems/)
# [Hammercores, Inc.](https://semiengineering.com/entities/hammercores-inc/)
# [HARDI Electronics AB](https://semiengineering.com/entities/hardi-electronics-ab/)
# [Harness Software Group](https://semiengineering.com/entities/harness-software-group/)
# [Hd Lab, K.K.](https://semiengineering.com/entities/hd-lab-k-k/)
# [HDAC Inc.](https://semiengineering.com/entities/hdac-inc/)
# [HDL Design House](https://semiengineering.com/entities/hdl-design-house/)
# [Helic, Inc.](https://semiengineering.com/entities/helic-inc/)
# [Helios Software Engineering Ltd.](https://semiengineering.com/entities/helios-software-engineering-ltd/)
# [Heterogeneous System Architecture (HSA) Foundation](https://semiengineering.com/entities/heterogeneous-system-architecture-hsa-foundation/)
# [Hewlett-Packard Company](https://semiengineering.com/entities/hewlett-packard-company/)
# [HHB assets](https://semiengineering.com/entities/hhb-assets/)
# [HHB Softron Inc.](https://semiengineering.com/entities/hhb-softron-inc/)
# [High Level Design Systems](https://semiengineering.com/entities/high-level-design-systems/)
# [HighIP Design Company](https://semiengineering.com/entities/highip-design-company/)
# [Hoschar AG](https://semiengineering.com/entities/hoschar-ag/)
# [HP Labs](https://semiengineering.com/entities/hp-labs/)
# [HPL Technologies, Inc.](https://semiengineering.com/entities/hpl-technologies-inc/)
# [Huins](https://semiengineering.com/entities/huins/)
# [Hunter and Ready](https://semiengineering.com/entities/hunter-and-ready/)
# [HyperLynx, Inc.](https://semiengineering.com/entities/hyperlynx-inc/)
# [IBM](https://semiengineering.com/entities/ibm/)
# [IBM â Altium group](https://semiengineering.com/entities/ibm-altium-group/)
# [IBM Foundry](https://semiengineering.com/entities/ibm-foundry/)
# [IC Manage](https://semiengineering.com/entities/ic-manage/)
# [ICScape, Inc.](https://semiengineering.com/entities/icscape-inc/)
# [ICUCOM Corporation](https://semiengineering.com/entities/icucom-corporation/)
# [IEC](https://semiengineering.com/entities/iec/)
# [IEEE](https://semiengineering.com/entities/ieee/)
# [IEEE 1800.2](https://semiengineering.com/entities/ieee-1800-2/)
# [IEEE DASC](https://semiengineering.com/entities/ieee-dasc/)
# [IEEE SA](https://semiengineering.com/entities/ieee-sa/)
# [IKOS Systems, Inc.](https://semiengineering.com/entities/ikos-systems-inc/)
# [Imagination Technologies](https://semiengineering.com/entities/imagination-technologies/)
# [Imec](https://semiengineering.com/entities/imec/)
# [iMODL](https://semiengineering.com/entities/imodl/)
# [Imperas Inc.](https://semiengineering.com/entities/imperas-inc/)
# [Impinj](https://semiengineering.com/entities/impinj/)
# [impinj NVM IP](https://semiengineering.com/entities/impinj-nvm-ip/)
# [IMS](https://semiengineering.com/entities/ims/)
# [In-Chip Systems](https://semiengineering.com/entities/in-chip-systems/)
# [INCASES Engineering GmbH](https://semiengineering.com/entities/incases-engineering-gmbh/)
# [Incentia Design Systems](https://semiengineering.com/entities/incentia-design-systems/)
# [Independent Design Automation Companies](https://semiengineering.com/entities/independent-design-automation-companies/)
# [Infineon Technologies](https://semiengineering.com/entities/infineon-technologies/)
# [Infiniscale](https://semiengineering.com/entities/infiniscale/)
# [Infinite Designs Ltd.](https://semiengineering.com/entities/infinite-designs-ltd/)
# [Ingenuus Corporation](https://semiengineering.com/entities/ingenuus-corporation/)
# [Ingot Systems](https://semiengineering.com/entities/ingot-systems/)
# [InnoLogic Systems, Inc.](https://semiengineering.com/entities/innologic-systems-inc/)
# [Innotech Corporation](https://semiengineering.com/entities/innotech-corporation/)
# [Innovative CAD Software, Inc.](https://semiengineering.com/entities/innovative-cad-software-inc/)
# [Innoveda, Inc.](https://semiengineering.com/entities/innoveda-inc/)
# [INRIA](https://semiengineering.com/entities/inria/)
# [inSilicon Corporation](https://semiengineering.com/entities/insilicon-corporation/)
# [InSpec Validation System](https://semiengineering.com/entities/inspec-validation-system/)
# [Instigate CJSC](https://semiengineering.com/entities/instigate-cjsc/)
# [Integrand Software](https://semiengineering.com/entities/integrand-software/)
# [Integrated Measurements Systems, Inc.](https://semiengineering.com/entities/integrated-measurements-systems-inc/)
# [Integrated Silicon Systems, Inc.](https://semiengineering.com/entities/integrated-silicon-systems-inc/)
# [Integrated Systems Engineering AG](https://semiengineering.com/entities/integrated-systems-engineering-ag/)
# [Integrity Engineering, Inc.](https://semiengineering.com/entities/integrity-engineering-inc/)
# [Intel Corp.](https://semiengineering.com/entities/intel-corp/)
# [Intel PLD business](https://semiengineering.com/entities/intel-pld-business/)
# [Intelligent Systems Japan, KK](https://semiengineering.com/entities/intelligent-systems-japan-kk/)
# [Intento Design](https://semiengineering.com/entities/intento-design/)
# [Interconnectix Inc.](https://semiengineering.com/entities/interconnectix-inc/)
# [Interfaces Technical Committee](https://semiengineering.com/entities/interfaces-technical-committee/)
# [Intergraph Electronics](https://semiengineering.com/entities/intergraph-electronics/)
# [Intergraph Inc.](https://semiengineering.com/entities/intergraph-inc/)
# [interHDL](https://semiengineering.com/entities/interhdl/)
# [Intermetrics](https://semiengineering.com/entities/intermetrics/)
# [Intermetrics VHDL simulator](https://semiengineering.com/entities/intermetrics-vhdl-simulator/)
# [International Organization of Standards](https://semiengineering.com/entities/international-organization-of-standards/)
# [Interra IT](https://semiengineering.com/entities/interra-it/)
# [InTime Software](https://semiengineering.com/entities/intime-software/)
# [Invarian, Inc.](https://semiengineering.com/entities/invarian-inc/)
# [Invarium, Inc.](https://semiengineering.com/entities/invarium-inc/)
# [Inventra](https://semiengineering.com/entities/inventra/)
# [Inventure Inc.](https://semiengineering.com/entities/inventure-inc/)
# [Invionics Inc.](https://semiengineering.com/entities/invionics-inc/)
# [IOTA Technology Inc.](https://semiengineering.com/entities/iota-technology-inc/)
# [IPextreme, Inc.](https://semiengineering.com/entities/ipextreme-inc/)
# [iRoC Technologies SA](https://semiengineering.com/entities/iroc-technologies-sa/)
# [ISSC Technology Corporation](https://semiengineering.com/entities/issc-technology-corporation/)
# [Japanese customers of Cadence software](https://semiengineering.com/entities/japanese-customers-of-cadence-software/)
# [Jasper Design Automation](https://semiengineering.com/entities/jasper-design-automation/)
# [Jazz Semiconductor, Inc.](https://semiengineering.com/entities/jazz-semiconductor-inc/)
# [JCET](https://semiengineering.com/entities/jcet/)
# [Jedat Inc.](https://semiengineering.com/entities/jedat-inc/)
# [JEDEC](https://semiengineering.com/entities/jedec/)
# [Juniper Networks, Inc.](https://semiengineering.com/entities/juniper-networks-inc/)
# [K2 Technologies, Inc.](https://semiengineering.com/entities/k2-technologies-inc/)
# [Kandou Bus](https://semiengineering.com/entities/kandou-bus/)
# [Keil](https://semiengineering.com/entities/keil/)
# [Keysight Technologies](https://semiengineering.com/entities/keysight-technologies/)
# [Kilopass Technology Inc.](https://semiengineering.com/entities/kilopass-technology-inc/)
# [Kimotion Technologies](https://semiengineering.com/entities/kimotion-technologies/)
# [KLA](https://semiengineering.com/entities/kla-tencor/)
# [KLA-Tencor](https://semiengineering.com/entities/kla-tencor-2/)
# [Knowlent Corporation](https://semiengineering.com/entities/knowlent-corporation/)
# [Kozio, Inc.](https://semiengineering.com/entities/kozio-inc/)
# [L-3 Communications](https://semiengineering.com/entities/l-3-communications/)
# [Lam Research](https://semiengineering.com/entities/lam-research/)
# [Lattice Semiconductor](https://semiengineering.com/entities/lattice-semiconductor/)
# [Leda Design, Inc.](https://semiengineering.com/entities/leda-design-inc/)
# [Leda SA](https://semiengineering.com/entities/leda-sa/)
# [Leuven Industrial Software Company](https://semiengineering.com/entities/leuven-industrial-software-company/)
# [Library Technologies, Inc.](https://semiengineering.com/entities/library-technologies-inc/)
# [Lighthouse Design Automation, Inc.](https://semiengineering.com/entities/lighthouse-design-automation-inc/)
# [Logic Automation, Inc.](https://semiengineering.com/entities/logic-automation-inc/)
# [Logic Modeling Corporation](https://semiengineering.com/entities/logic-modeling-corporation/)
# [Logic Modeling Systems Inc.](https://semiengineering.com/entities/logic-modeling-systems-inc/)
# [Logical Devices, Inc.](https://semiengineering.com/entities/logical-devices-inc/)
# [LogicVision, Inc.](https://semiengineering.com/entities/logicvision-inc/)
# [Logipard AB](https://semiengineering.com/entities/logipard-ab/)
# [Looking Glass Studios](https://semiengineering.com/entities/looking-glass-studios/)
# [Lorentz Solution, Inc.](https://semiengineering.com/entities/lorentz-solution-inc/)
# [LSI Logic](https://semiengineering.com/entities/lsi-logic/)
# [Luminescent Mask Synthesis technology](https://semiengineering.com/entities/luminescent-mask-synthesis-technology/)
# [Luminescent Technologies](https://semiengineering.com/entities/luminescent-technologies/)
# [Magillem](https://semiengineering.com/entities/magillem/)
# [Magma Design Automation Inc.](https://semiengineering.com/entities/magma-design-automation-inc/)
# [Magwel NV](https://semiengineering.com/entities/magwel-nv/)
# [Marple Technologies](https://semiengineering.com/entities/marple-technologies/)
# [Marvell Technology](https://semiengineering.com/entities/marvell-technology-group-ltd/)
# [Massachusetts Institute of Technology](https://semiengineering.com/entities/massachusetts-institute-of-technology/)
# [Massteck Ltd.](https://semiengineering.com/entities/massteck-ltd/)
# [Mathtools Ltd](https://semiengineering.com/entities/mathtools-ltd/)
# [Mathworks](https://semiengineering.com/entities/mathworks/)
# [Maxim Integrated Inc.](https://semiengineering.com/entities/maxim-integrated-inc/)
# [Memory BIST Division of iRoC](https://semiengineering.com/entities/memory-bist-division-of-iroc/)
# [Menta](https://semiengineering.com/entities/menta/)
# [Mentor Embedded Systems Division](https://semiengineering.com/entities/mentor-embedded-systems-division/)
# [Mentor Emulation Division](https://semiengineering.com/entities/mentor-emulation-division/)
# [Mentor Mechanical Analysis Division](https://semiengineering.com/entities/mentor-mechanical-analysis-division/)
# [Mentor physical libraries](https://semiengineering.com/entities/mentor-physical-libraries/)
# [Mercel AB](https://semiengineering.com/entities/mercel-ab/)
# [Mercel AUTOSAR assets](https://semiengineering.com/entities/mercel-autosar-assets/)
# [Meropa Inc.](https://semiengineering.com/entities/meropa-inc/)
# [Meta Systems SARL](https://semiengineering.com/entities/meta-systems-sarl/)
# [Meta-Software Inc.](https://semiengineering.com/entities/meta-software-inc/)
# [Metamor Inc.](https://semiengineering.com/entities/metamor-inc/)
# [MetaWare Inc.](https://semiengineering.com/entities/metaware-inc/)
# [Methodics, Inc.](https://semiengineering.com/entities/methodics-inc/)
# [Micro Magic EDA assets](https://semiengineering.com/entities/micro-magic-eda-assets/)
# [Micro Magic, Inc.](https://semiengineering.com/entities/micro-magic-inc/)
# [Microchip Technology, Inc.](https://semiengineering.com/entities/microchip-technology-inc/)
# [Microcode Engineering Inc.](https://semiengineering.com/entities/microcode-engineering-inc/)
# [Microcosm Technologies Inc.](https://semiengineering.com/entities/microcosm-technologies-inc/)
# [Microelectronics Research & Development Ltd.](https://semiengineering.com/entities/microelectronics-research-development-ltd/)
# [Micrologic Solutions Limited](https://semiengineering.com/entities/micrologic-solutions-limited/)
# [Microsemi Corporation](https://semiengineering.com/entities/microsemi-corporation/)
# [MicroSim Corp](https://semiengineering.com/entities/microsim-corp/)
# [Microtec Research, Inc.](https://semiengineering.com/entities/microtec-research-inc/)
# [Microtronic](https://semiengineering.com/entities/microtronic/)
# [Mint Technology](https://semiengineering.com/entities/mint-technology/)
# [MIPI Alliance](https://semiengineering.com/entities/mipi-alliance/)
# [MIPS Analog Business Group](https://semiengineering.com/entities/mips-analog-business-group/)
# [MIPS Technologies](https://semiengineering.com/entities/mips-technologies/)
# [Mirabilis Design](https://semiengineering.com/entities/mirabilis-design/)
# [Missing Link Tools](https://semiengineering.com/entities/missing-link-tools/)
# [MITRE Engenuity](https://semiengineering.com/entities/mitre-engenuity/)
# [Mitsui Bussan Digital Corp](https://semiengineering.com/entities/mitsui-bussan-digital-corp/)
# [Mixel, Inc.](https://semiengineering.com/entities/mixel-inc/)
# [Mobiveil, Inc.](https://semiengineering.com/entities/mobiveil-inc/)
# [Model Technology Inc.](https://semiengineering.com/entities/model-technology-inc/)
# [Modus Test](https://semiengineering.com/entities/modus-test/)
# [Mojave, Inc.](https://semiengineering.com/entities/mojave-inc/)
# [MonolithIC 3D Inc](https://semiengineering.com/entities/monolithic-3d-inc/)
# [Monterey Design Systems, Inc.](https://semiengineering.com/entities/monterey-design-systems-inc/)
# [Moortec Semiconductor Ltd.](https://semiengineering.com/entities/moortec-semiconductor-ltd/)
# [Morfik Technology Pty Ltd.](https://semiengineering.com/entities/morfik-technology-pty-ltd/)
# [MOSAID SIP assets](https://semiengineering.com/entities/mosaid-sip-assets/)
# [MOSAID Technologies Inc.](https://semiengineering.com/entities/mosaid-technologies-inc/)
# [Moscape, Inc](https://semiengineering.com/entities/moscape-inc/)
# [MOSIS](https://semiengineering.com/entities/mosis/)
# [Mosys SerDes IP](https://semiengineering.com/entities/mosys-serdes-ip/)
# [MoSys, Inc.](https://semiengineering.com/entities/mosys-inc/)
# [Movellus](https://semiengineering.com/entities/movellus/)
# [Multicore Association](https://semiengineering.com/entities/multicore-association/)
# [MunEDA GmbH](https://semiengineering.com/entities/muneda-gmbh/)
# [NanGate, Inc.](https://semiengineering.com/entities/nangate-inc/)
# [Nannor Technologies Inc.](https://semiengineering.com/entities/nannor-technologies-inc/)
# [Nascentric, Inc.](https://semiengineering.com/entities/nascentric-inc/)
# [Nassda Corporation](https://semiengineering.com/entities/nassda-corporation/)
# [National Research Council of Canada](https://semiengineering.com/entities/national-research-council-of-canada/)
# [National Semiconducor](https://semiengineering.com/entities/national-semiconducor/)
# [Neolinear, Inc.](https://semiengineering.com/entities/neolinear-inc/)
# [NetSpeed Systems](https://semiengineering.com/entities/netspeed-systems/)
# [Network Design Tools, Inc.](https://semiengineering.com/entities/network-design-tools-inc/)
# [NeuroCAD Inc.](https://semiengineering.com/entities/neurocad-inc/)
# [Nexsyn Design Technology Inc](https://semiengineering.com/entities/nexsyn-design-technology-inc/)
# [Next Device Limited](https://semiengineering.com/entities/next-device-limited/)
# [NextOp Software, Inc.](https://semiengineering.com/entities/nextop-software-inc/)
# [NI (formerly National Instruments)](https://semiengineering.com/entities/national-instruments/)
# [Nimbic, Inc.](https://semiengineering.com/entities/nimbic-inc/)
# [NM Electronics](https://semiengineering.com/entities/nm-electronics/)
# [Northwest Logic, Inc.](https://semiengineering.com/entities/northwest-logic-inc/)
# [Nova](https://semiengineering.com/entities/nova/)
# [Novarm Limited](https://semiengineering.com/entities/novarm-limited/)
# [Novas Software](https://semiengineering.com/entities/novas-software/)
# [Novelics](https://semiengineering.com/entities/novelics/)
# [Novo Systems Corp](https://semiengineering.com/entities/novo-systems-corp/)
# [Novocell Semiconductor, Inc.](https://semiengineering.com/entities/novocell-semiconductor-inc/)
# [NP Komplete Technologies BV](https://semiengineering.com/entities/np-komplete-technologies-bv/)
# [nSys Design Systems Private Limited](https://semiengineering.com/entities/nsys-design-systems-private-limited/)
# [Numerical Technologies, Inc.](https://semiengineering.com/entities/numerical-technologies-inc/)
# [NuPGA](https://semiengineering.com/entities/nupga/)
# [Nusym Technology, Inc.](https://semiengineering.com/entities/nusym-technology-inc/)
# [NXP CMOS IP](https://semiengineering.com/entities/nxp-cmos-ip/)
# [NXP Semiconductor](https://semiengineering.com/entities/nxp-semiconductor/)
# [Oasys Design Systems Inc.](https://semiengineering.com/entities/oasys-design-systems-inc/)
# [Obsidian Software](https://semiengineering.com/entities/obsidian-software/)
# [OCP-IP](https://semiengineering.com/entities/ocp-ip/)
# [Omnicad Corp.](https://semiengineering.com/entities/omnicad-corp/)
# [OneSpin Solutions GmbH](https://semiengineering.com/entities/onespin-solutions-gmbh/)
# [Onto Innovation](https://semiengineering.com/entities/onto-innovation/)
# [OPC Technology](https://semiengineering.com/entities/opc-technology/)
# [Open Networks Engineering](https://semiengineering.com/entities/open-networks-engineering/)
# [Open SystemC Initiative](https://semiengineering.com/entities/open-systemc-initiatve/)
# [Open Verilog International](https://semiengineering.com/entities/open-verilog-international/)
# [Open Virtual Platforms](https://semiengineering.com/entities/open-virtual-platforms/)
# [Open-Silicon, Inc.](https://semiengineering.com/entities/open-silicon-inc/)
# [OptEM Engineering Inc.](https://semiengineering.com/entities/optem-engineering-inc/)
# [Optic2Connect Pte Ltd](https://semiengineering.com/entities/optic2connect-pte-ltd/)
# [Optical Internetworking Forum (OIF)](https://semiengineering.com/entities/optical-internetworking-forum-oif/)
# [Optical Research Associates LLC](https://semiengineering.com/entities/optical-research-associates-llc/)
# [Optimal Corporation](https://semiengineering.com/entities/optimal-corporation/)
# [Optimal Solutions, Inc.](https://semiengineering.com/entities/optimal-solutions-inc/)
# [OptimalPlus](https://semiengineering.com/entities/optimal-plus/)
# [OrCAD](https://semiengineering.com/entities/orcad/)
# [Oski Technology](https://semiengineering.com/entities/oski-technology/)
# [Out of Business](https://semiengineering.com/entities/out-of-business/)
# [Pacer Infotec Inc.](https://semiengineering.com/entities/pacer-infotec-inc/)
# [PADS Software Inc.](https://semiengineering.com/entities/pads-software-inc/)
# [Palmchip Corporation](https://semiengineering.com/entities/palmchip-corporation/)
# [Palmchip interface IP](https://semiengineering.com/entities/palmchip-interface-ip/)
# [Panel Level Packaging Consortium (PLC)](https://semiengineering.com/entities/panel-level-packaging-consortium-plc/)
# [Paradigm Works](https://semiengineering.com/entities/paradigm-works/)
# [Parsec Software Inc.](https://semiengineering.com/entities/parsec-software-inc/)
# [PCB Libraries Inc.](https://semiengineering.com/entities/pcb-libraries-inc/)
# [PCB Matrix Corporation](https://semiengineering.com/entities/pcb-matrix-corporation/)
# [PDF Solutions](https://semiengineering.com/entities/pdf-solutions/)
# [Performance CAD](https://semiengineering.com/entities/performance-cad/)
# [Performance Signal Integrity, Inc.](https://semiengineering.com/entities/performance-signal-integrity-inc/)
# [Performance-IP, LLC.](https://semiengineering.com/entities/performance-ip-llc/)
# [Personal CAD Systems](https://semiengineering.com/entities/personal-cad-systems/)
# [Pextra Corporation](https://semiengineering.com/entities/pextra-corporation/)
# [Philips Semiconductor](https://semiengineering.com/entities/philips-semiconductor/)
# [Phoenix Technologies Ltd.](https://semiengineering.com/entities/phoenix-technologies-ltd/)
# [Physware, Inc.](https://semiengineering.com/entities/physware-inc/)
# [PiE Design Systems Inc.](https://semiengineering.com/entities/pie-design-systems-inc/)
# [Pinebush Technologies](https://semiengineering.com/entities/pinebush-technologies/)
# [Plato Design Systems](https://semiengineering.com/entities/plato-design-systems/)
# [PLDA](https://semiengineering.com/entities/plda/)
# [Pleiades Design and Test Technologies Inc.](https://semiengineering.com/entities/pleiades-design-and-test-technologies-inc/)
# [Plunify Pte Ltd](https://semiengineering.com/entities/plunify-pte-ltd/)
# [Pollen Technology](https://semiengineering.com/entities/pollen-technology/)
# [PolySpace Technologies](https://semiengineering.com/entities/polyspace-technologies/)
# [Ponte Solutions Inc.](https://semiengineering.com/entities/ponte-solutions-inc/)
# [Portable Stimulus Working Group (PSWG)](https://semiengineering.com/entities/portable-stimulus-working-group/)
# [PowerEscape, Inc.](https://semiengineering.com/entities/powerescape-inc/)
# [Praesagus, Inc.](https://semiengineering.com/entities/praesagus-inc/)
# [Precedence Inc.](https://semiengineering.com/entities/precedence-inc/)
# [Precim Corp](https://semiengineering.com/entities/precim-corp/)
# [Precise Software Technologies Inc](https://semiengineering.com/entities/precise-software-technologies-inc/)
# [ProDesign Electronic GmbH](https://semiengineering.com/entities/prodesign-electronic-gmbh/)
# [Progressant Technologies, Inc.](https://semiengineering.com/entities/progressant-technologies-inc/)
# [Project Technology Inc.](https://semiengineering.com/entities/project-technology-inc/)
# [Prolific, Inc.](https://semiengineering.com/entities/prolific-inc/)
# [Promex Industries](https://semiengineering.com/entities/promex-industries/)
# [ProPlus Design Solutions, Inc.](https://semiengineering.com/entities/proplus-design-solutions-inc/)
# [ProSoft Oy](https://semiengineering.com/entities/prosoft-oy/)
# [proteanTecs](https://semiengineering.com/entities/proteantecs/)
# [Protecode](https://semiengineering.com/entities/protecode/)
# [Protel International Pty, Ltd.](https://semiengineering.com/entities/protel-international-pty-ltd/)
# [Provis Corporation](https://semiengineering.com/entities/provis-corporation/)
# [prpl foundation](https://semiengineering.com/entities/prpl-foundation/)
# [Pulsic](https://semiengineering.com/entities/pulsic/)
# [Pyxis Technology](https://semiengineering.com/entities/pyxis-technology/)
# [Q Design Automation](https://semiengineering.com/entities/q-design-automation/)
# [Q Point Technology](https://semiengineering.com/entities/q-point-technology/)
# [QP Technologies](https://semiengineering.com/entities/quik-pak/)
# [QPX GmbH](https://semiengineering.com/entities/qpx-gmbh/)
# [Quad Design Technology, Inc.](https://semiengineering.com/entities/quad-design-technology-inc/)
# [Quadric](https://semiengineering.com/entities/quadric/)
# [Quadtree Software Corporation](https://semiengineering.com/entities/quadtree-software-corporation/)
# [Qualcomm Incorporated](https://semiengineering.com/entities/qualcomm-incorporated/)
# [Qualis, Inc.](https://semiengineering.com/entities/qualis-inc/)
# [Quickturn Design Systems, Inc.](https://semiengineering.com/entities/quickturn-design-systems-inc/)
# [R3Logic, Inc.](https://semiengineering.com/entities/r3logic-inc/)
# [Racal Redac](https://semiengineering.com/entities/racal-redac/)
# [Racal Redac â VHDL simulator](https://semiengineering.com/entities/racal-redac-vhdl-simulator/)
# [Racal Redac SilcSyn](https://semiengineering.com/entities/racal-redac-silcsyn/)
# [Radiant Design Tools, Inc.](https://semiengineering.com/entities/radiant-design-tools-inc/)
# [Rambus, Inc.](https://semiengineering.com/entities/rambus-inc/)
# [Random Logic Corporation](https://semiengineering.com/entities/random-logic-corporation/)
# [RAPID](https://semiengineering.com/entities/rapid/)
# [RaveSim, Inc.](https://semiengineering.com/entities/ravesim-inc/)
# [RAVIcad Inc.](https://semiengineering.com/entities/ravicad-inc/)
# [Ready Systems](https://semiengineering.com/entities/ready-systems/)
# [Real Intent, Inc.](https://semiengineering.com/entities/real-intent-inc/)
# [Redwood Design Automation](https://semiengineering.com/entities/redwood-design-automation/)
# [Renesas Electronics](https://semiengineering.com/entities/renesas-electronics/)
# [ReShape Inc](https://semiengineering.com/entities/reshape-inc/)
# [RevoSys Inc.](https://semiengineering.com/entities/revosys-inc/)
# [Right Track CAD Corp.](https://semiengineering.com/entities/right-track-cad-corp/)
# [Rio Design Automation](https://semiengineering.com/entities/rio-design-automation/)
# [Riscure](https://semiengineering.com/entities/riscure/)
# [RivieraWaves](https://semiengineering.com/entities/rivierawaves/)
# [Rocketick](https://semiengineering.com/entities/rocketick/)
# [Router Soutions, Inc.](https://semiengineering.com/entities/router-soutions-inc/)
# [Royal Digital Centers, Inc.](https://semiengineering.com/entities/royal-digital-centers-inc/)
# [RSoft Design Group Inc.](https://semiengineering.com/entities/rsoft-design-group-inc/)
# [Runtime Design Automation](https://semiengineering.com/entities/runtime-design-automation/)
# [S2C Inc.](https://semiengineering.com/entities/s2c-inc/)
# [S3 Group](https://semiengineering.com/entities/s3-group/)
# [Sabio Labs](https://semiengineering.com/entities/sabio-labs/)
# [Safelogic](https://semiengineering.com/entities/safelogic/)
# [Sagantec](https://semiengineering.com/entities/sagantec/)
# [Sage Design Automation, Inc.](https://semiengineering.com/entities/sage-design-automation-inc/)
# [Samsung Semiconductor](https://semiengineering.com/entities/samsung-foundry/)
# [Sand Microelectronics](https://semiengineering.com/entities/sand-microelectronics/)
# [Sandburst](https://semiengineering.com/entities/sandburst/)
# [Sandwork Design, Inc.](https://semiengineering.com/entities/sandwork-design-inc/)
# [Sankalp Semiconductor](https://semiengineering.com/entities/sankalp-semiconductor/)
# [SCALD Corporation](https://semiengineering.com/entities/scald-corporation/)
# [SciFace Software GmbH & Co. KG](https://semiengineering.com/entities/sciface-software-gmbh-co-kg/)
# [SDA Systems Inc.](https://semiengineering.com/entities/sda-systems-inc/)
# [Sedco](https://semiengineering.com/entities/sedco/)
# [See Technologies](https://semiengineering.com/entities/see-technologies/)
# [Seed Solutions Inc.](https://semiengineering.com/entities/seed-solutions-inc/)
# [SEMI](https://semiengineering.com/entities/semi/)
# [Semiconductor Manufacturing International Corp.](https://semiengineering.com/entities/semiconductor-manufacturing-international-corp/)
# [Semifore, Inc.](https://semiengineering.com/entities/semifore-inc/)
# [Sente Inc.](https://semiengineering.com/entities/sente-inc/)
# [Sequence Design](https://semiengineering.com/entities/sequence-design/)
# [SETO Software GmbH](https://semiengineering.com/entities/seto-software-gmbh/)
# [Shiva Multisystems Corp.](https://semiengineering.com/entities/shiva-multisystems-corp/)
# [Si2](https://semiengineering.com/entities/si2/)
# [Si2 Open3D Technical Advisory Board](https://semiengineering.com/entities/si2-open3d-technical-advisory-board/)
# [Sibridge Technologies](https://semiengineering.com/entities/sibridge-technologies/)
# [SiCAD Inc.](https://semiengineering.com/entities/sicad-inc/)
# [Sidense Corp.](https://semiengineering.com/entities/sidense-corp/)
# [Siemens EDA](https://semiengineering.com/entities/mentor-a-siemens-business/)
# [Sierra Design Automation](https://semiengineering.com/entities/sierra-design-automation/)
# [Sigma-C Software AG](https://semiengineering.com/entities/sigma-c-software-ag/)
# [Signal Integrity Software, Inc.](https://semiengineering.com/entities/signal-integrity-software-inc/)
# [Signetics Corporation](https://semiengineering.com/entities/signetics-corporation/)
# [Sigrity, Inc.](https://semiengineering.com/entities/sigrity-inc/)
# [SilabTech Pvt Ltd.](https://semiengineering.com/entities/silabtech-pvt-ltd/)
# [Silc Technologies](https://semiengineering.com/entities/silc-technologies/)
# [Silerity Inc](https://semiengineering.com/entities/silerity-inc/)
# [Silexica](https://semiengineering.com/entities/silexica/)
# [Silicon Architects](https://semiengineering.com/entities/silicon-architects/)
# [Silicon Canvas, Inc.](https://semiengineering.com/entities/silicon-canvas-inc/)
# [Silicon Cloud International Pte Ltd](https://semiengineering.com/entities/silicon-cloud-international-pte-ltd/)
# [Silicon Compiler Systems Corp.](https://semiengineering.com/entities/silicon-compiler-systems-corp/)
# [Silicon Compilers Inc.](https://semiengineering.com/entities/silicon-compilers-inc/)
# [Silicon Creations, LLC](https://semiengineering.com/entities/silicon-creations-llc/)
# [Silicon Design Labs](https://semiengineering.com/entities/silicon-design-labs/)
# [Silicon Design Solutions](https://semiengineering.com/entities/silicon-design-solutions/)
# [Silicon Forest Research inc.](https://semiengineering.com/entities/silicon-forest-research-inc/)
# [Silicon Frontline Technology, Inc.](https://semiengineering.com/entities/silicon-frontline-technology-inc/)
# [Silicon Logic Engineering](https://semiengineering.com/entities/silicon-logic-engineering/)
# [Silicon Metrics Corporation](https://semiengineering.com/entities/silicon-metrics-corporation/)
# [Silicon Perspective Corp.](https://semiengineering.com/entities/silicon-perspective-corp/)
# [Silicon Solutions Corporation](https://semiengineering.com/entities/silicon-solutions-corporation/)
# [Silicon Sorcery](https://semiengineering.com/entities/silicon-sorcery/)
# [Silicon Storage Technology, Inc.](https://semiengineering.com/entities/silicon-storage-technology-inc/)
# [Silicon Valley Research](https://semiengineering.com/entities/silicon-valley-research/)
# [Silicon West](https://semiengineering.com/entities/silicon-west/)
# [SiliconBlue Technologies Corporation](https://semiengineering.com/entities/siliconblue-technologies-corporation/)
# [SiliconGate LDA](https://semiengineering.com/entities/silicongate-lda/)
# [Siliconware Precision Industries](https://semiengineering.com/entities/siliconware-precision-industries/)
# [Silvaco, Inc.](https://semiengineering.com/entities/silvaco-inc/)
# [Silvar-Lisco, Inc.](https://semiengineering.com/entities/silvar-lisco-inc/)
# [Simon Software](https://semiengineering.com/entities/simon-software/)
# [Simpleware](https://semiengineering.com/entities/simpleware/)
# [Simplex Solutions](https://semiengineering.com/entities/simplex-solutions/)
# [Simucad Design Automation Inc.](https://semiengineering.com/entities/simucad-design-automation-inc/)
# [Simucad Inc.](https://semiengineering.com/entities/simucad-inc/)
# [Simulation Technologies Corp](https://semiengineering.com/entities/simulation-technologies-corp/)
# [SimuQuest, Inc.](https://semiengineering.com/entities/simuquest-inc/)
# [Simutech Corporation](https://semiengineering.com/entities/simutech-corporation/)
# [SiVerion, Inc.](https://semiengineering.com/entities/siverion-inc/)
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| Readable Markdown | ## [2\.5D](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/2-5d-ic/)
Multiple chips arranged in a planar or stacked configuration with an interposer for communication.
## [2D Materials](https://semiengineering.com/knowledge_centers/materials/2d-materials/)
## [3D NAND](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/flash-memory/3d-nand/)
Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.
But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.
Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.
In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.
In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.
One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.
The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.
Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.
Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.
Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a âmacaroni channel,â according to Objective Analysis.
Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.
Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.
## [3D Transistors](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/)
Transistors where source and drain are added as fins of the gate.
## [3D-ICs](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/3d-ics/)
2\.5D and 3D forms of integration
## [5G](https://semiengineering.com/knowledge_centers/data-movement/wireless/5g/)
Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.
## [6G](https://semiengineering.com/knowledge_centers/data-movement/wireless/6g/)
## [A brief history of design](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design/a-brief-history-of-design/)
We start with schematics and end with ESL
## [A brief history of logic simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/a-brief-history-of-logic-simulation/)
Important events in the history of logic simulation
## [A brief history of logic synthesis](https://semiengineering.com/knowledge_centers/eda-design/definitions/a-brief-history-of-logic-synthesis/)
Early development associated with logic synthesis
## [Acronyms](https://semiengineering.com/knowledge_centers/acronyms/)
Commonly and not-so-commonly used acronyms.
The following is a list of acronyms and what they stand for:
ACK - Acknowledge
ADC - Analog to Digital Converter
AI - Artificial Intelligence
ALD - Atomic Layer Deposition
ALE - Atomic Layer Etch
AMOLED - Active-Matrix OLED
AMP - Asymmetric Multi Processing
AOI - Automated Optical Inspection
AP - Access Point
ASIC - Application Specific Integrated Circuit
ATE - Automatic Test Equipment
BEOL - Back-End-Of-Line
BGA - Ball Grid Array
BSA - Basic Service Area
BTI - Bias-Temperature Instability
CA - Collision Avoidance
CBRAM - Conductive Bridging RAM
CCI - Cache Coherent Interconnect
CD Collision Detection
CF - Contention-Free
CFP - Contention-Free Period
CP - Contention Period
CPU - Central Processing Unit
CRC - Cyclic Redundancy Check
CSMA - Carrier Sense, Multiple Access
CFD - Computational Fluid Dynamic
CMOS - Complementary Metal Oxide Semiconductor
CNN - Convolutional Neural Network
CPP - Contacted Poly Pitch
CSP - Chip Scale Packaging
CTS - Clear To Send
DAC - Digital to Analog Convertor
DARPA - Defense Advanced Research Projects Agency
DCF - Distributed Coordination Function
DDR - Double Data Rate
DFA - Differential Fault Analysis
DFT - Design for Test
DFM - Design for Manufacturing
DIFS - Distributed Inter-frame Space
DPA - Differential Power Analysis
DL - Deep Learning
DRAM - Dynamic Random Access Memory
DRC - Design Rule Checker
DSA - Directed Self Assembly
DSP - Digital Signal Processor
DUT - Design Under Test
DUV - Design Under Verification
DVFS - Dynamic Voltage and Frequency Scaling
ECO - Engineering Change Order
EDA - Electronic Design Automation
EM - Electromagnetic
EM - Electromigration
ESL - Electronic System Level
EUV - Extreme Ultraviolet
FD-SOI - Fully Depleted Silicon on Insulator
FEOL - Front-End-Of-Line
FET - Field Effect Transistor
FIFO - First In First Out
FPGA - Field Programmable Gate Array
GAA - Gate-All-Around
GaAs - Gallium Arsenide
GaN - Gallium Nitride
GPU - Graphics Processing Unit
HBM - High Bandwidth Memory
HBT - Heterojunction Bipolar Transistor
HDL - Hardware Description Language
HMC - Hybrid Memory Cube
IC - Integrated Circuit
IEEE - Institute of Electrical and Electronics Engineers
IIC - Industrial Internet Consortium
IIoT - Industrial Internet of Things
IoT - Internet of Things
IP - Intellectual Property
IR - Infra-red
ISM - Industrial, Scientific, Medical
ISS - Instruction Set Simulator
ILT - Inverse Lithography Technology
JTAG - Joint Test Action Group
LAN - Local Area Network
LCD - Liquid Crystal Display
LTE - Long-Term Evolution
MAC -Media Access Control
MCU - Microcontroller
MEMS - Micro Electrical Mechanical Systems
MES - Manufacturing Execution Systems
ML-Machine Learning
MOL - Middle-Of-Line
MRAM - Magnetic Random Access Memory
NA - Numerical Aperture
NGL - Next-Generation Lithography
NIC - Network Interface Card
NSF - National Science Foundation
NVM - Non-Volatile Memory
OCAP - Out of Control Action Plan
OLED - Organic Light-Emitting Diode
OPC - Optical Proximity Correction
OS - Operating System
OSAT - Outsourced Semiconductor Assembly and Test
OTP - One Time Programmable
PCB - Printed Circuit Board
PCF - Point Coordination Function
PCM - Phase-Change Memory
PDK - Process Design Kit
PDN - Power Delivery Network
PHY - Physical Layer
PI - Power Integrity
PIFS - Point Inter-frame Space
PnR - Place and Route
PoP - Package-on-Package
PPA - Power, Performance, Area
PPAC - Power, Performance, Area, Cost
PRNG - Pure Random Number Generator
PVT - Process, Voltage, Temperature
RAM - Random Access Memory
RC4 - Rivest Cipher 4
RDL - Register Definition Language
RDL - Redistribution Layer
RF - Radio Frequency
ROM - Read Only Memory
RoT - Root Of Trust
RTL - Register Transfer Level
RTOS - Real Time Operating System
RTS - Request To Send
SCM - Storage Class Memory
SerDes - Serializer / Deserializer
SIFS - Short Inter-frame Space
SI - Signal Integrity
SiC - Silicon Carbide
SiGe - Silicon Germanium
SK - Shared Key
SMP - Symmetric Multi Processing
SoC - System on Chip
SOI - Silicon on Insulator
SPA - Simple Power Analysis
SRAF - Sub-Resolution Assist Features
SRAM - Static Random Access Memory
SSD - Solid-state Storage Drives
SSID - Service Set Identifier
STA - Static Timing Analysis
STI - Shallow Trench Isolation
TLM - Transaction Level Model
TSV - Through Silicon Via
UPF - Unified Power Format
USB - Universal Serial Bus
UVM - Universal Verification Methodology
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
VSLI - Very Large Scale Integration
VIP - Verification Intellectual Property
VoWi-Fi - Voice over Wi-Fi
Vt - theshold Voltage
Wan - Wide Area Network
WEP - Wired Equivalency Protocol
Wi-Fi - Wireless High Fidelity
WiGIG - Gigabit Wi-Fi
WLAN - Wireless Local Area Network
WLP - Wafer Level Packaging
WPA - Wi-Fi Protected Access
## [ADAS: Advanced Driver Assistance Systems](https://semiengineering.com/knowledge_centers/automotive/adas-advanced-driver-assistance-systems/)
Sensing and processing to make driving safer.
## [Advanced Packaging](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/)
Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.
While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.
These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.
## [Advanced Packaging Fundamentals eBook (2025-2026)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/ebook-advanced-packaging-fundamentals/)
## [Agile](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/agile/)
An approach to software development focusing on continual delivery and flexibility to changing requirements
## [Agile Hardware Development](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/agile/agile-hardware-development/)
How Agile applies to the development of hardware systems
## [Air Gap](https://semiengineering.com/knowledge_centers/manufacturing/process/air-gap/)
A way of improving the insulation between various components in a semiconductor by creating empty space.
## [Amdahlâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/amdahls-law/)
The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.
## [Analog](https://semiengineering.com/knowledge_centers/eda-design/definitions/analog/)
Semiconductors that measure real-world conditions
## [Analog circuits](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/analog-circuits/)
Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.
## [Analog Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/definitions/analog/analog-design-and-verification/)
The design and verification of analog components.
## [Application Programming Interface (API)](https://semiengineering.com/knowledge_centers/user-interfaces/application-programming-interface-api/)
A software tool used in software programming that abstracts all the programming steps into a user interface for the developer.
## [Application Specific Integrated Circuit (ASIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/application-specific-integrated-circuit-asic/)
A custom, purpose-built integrated circuit made for a specific task or product.
## [Application-Specific Standard Product (ASSP)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/assp-application-specific-standard-product/)
An IC created and optimized for a market and sold to multiple companies.
## [Architectures](https://semiengineering.com/knowledge_centers/compute-architectures/)
## [Artificial Intelligence (AI)](https://semiengineering.com/knowledge_centers/artificial-intelligence/)
Using machines to make decisions based upon stored knowledge and sensory input.
## [Assertion](https://semiengineering.com/knowledge_centers/eda-design/verification/formal-verification/assertion/)
Code that looks for violations of a property
## [Atomic Force Microscopy (AFM), Atomic Force Microscope (AFM)](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/atomic-force-microscopy-afm-atomic-force-microscope-afm/)
A method of measuring the surface structures down to the angstrom level.
## [Atomic Layer Deposition (ALD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/atomic-layer-deposition/)
A method of depositing materials and films in exact places on a surface.
## [Atomic Layer Etch (ALE)](https://semiengineering.com/knowledge_centers/manufacturing/process/atomic-layer-etch/)
ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.
## [Automatic Test Equipment (ATE)](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/automatic-test-equipment-ate/)
## [Automatic Test Pattern Generation (ATPG)](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/)
The generation of tests that can be used for functional or manufacturing verification
## [Automotive](https://semiengineering.com/knowledge_centers/automotive/)
Issues dealing with the development of automotive electronics.
## [Automotive Ethernet, Time Sensitive Networking (TSN)](https://semiengineering.com/knowledge_centers/automotive/automotive-ethernet-time-sensitive-networking-tsn/)
Time sensitive networking puts real time into automotive Ethernet.
## [Automotive Standards](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/)
## [Autonomous Vehicles](https://semiengineering.com/knowledge_centers/automotive/autonomous-vehicles/)
## [Avalanche Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/avalanche-noise/)
Noise in reverse biased junctions
## [AVM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/avm/)
Verification methodology created by Mentor
## [Backend-of-the-line (BEOL)](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/)
IC manufacturing processes where interconnects are made.
## [Backside Power Delivery Network (BPDN)](https://semiengineering.com/knowledge_centers/low-power/backside-power-delivery-network/)
## [Bandgap, Band Gap](https://semiengineering.com/knowledge_centers/materials/band-gap/)
## [Batteries](https://semiengineering.com/knowledge_centers/low-power/batteries/)
Devices that chemically store energy.
## [Behavioral Synthesis](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/behavioral-synthesis/)
Transformation of a design described in a high-level of abstraction to RTL
## [Blech Effect](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/blech-effect/)
A reverse force to electromigration.
## [Bluetooth, Bluetooth Low Energy (BLE)](https://semiengineering.com/knowledge_centers/data-movement/wireless/bluetooth-low-energy-2/)
Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.
## [Brazil](https://semiengineering.com/knowledge_centers/regional-developments-issues/brazil/)
## [BSIM](https://semiengineering.com/knowledge_centers/eda-design/models/bsim/)
Transistor model
## [Built-in self-test (BiST)](https://semiengineering.com/knowledge_centers/test/built-in-self-test-bist/)
On-chip logic to test a design.
## [Bunch of Wires (BoW)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/bunch-of-wires-bow/)
Chiplet interconnect specification.
## [Bus Functional Model](https://semiengineering.com/knowledge_centers/eda-design/models/bus-functional-model/)
Interface model between testbench and device under test
## [C, C++](https://semiengineering.com/knowledge_centers/languages/c-c/)
C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.
## [Cache Coherent Interconnect for Accelerators (CCIX)](https://semiengineering.com/knowledge_centers/standards-laws/standards/cache-coherent-interconnect-for-accelerators-ccix/)
Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.
## [CD-SEM: Critical-Dimension Scanning Electron Microscope](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/cd-sem/)
CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.
## [CDC design principles](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/cdc-design-principles/)
Making CDC interfaces predictable
## [Cell-Aware Test](https://semiengineering.com/knowledge_centers/test/cell-aware-test/)
Fault model for faults within cells
## [Cell-Aware Test for FinFET](https://semiengineering.com/knowledge_centers/test/cell-aware-test/cell-aware-test-for-finfet/)
Cell-aware test methodology for addressing defect mechanisms specific to FinFETs.
## [Central Processing Unit (CPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/central-processing-unit-cpu/)
The CPU is an dedicated integrated circuit or IP core that processes logic and math.
## [Characterization/Metrology Lab](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/characterization-metrology-lab/)
A lab that wrks with R\&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.
## [Checker](https://semiengineering.com/knowledge_centers/eda-design/verification/checker/)
Testbench component that verifies results
## [Chemical Vapor Deposition (CVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/chemical-vapor-deposition/)
A process used to develop thin films and polymer coatings.
## [China](https://semiengineering.com/knowledge_centers/regional-developments-issues/china/)
## [Chip Design](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design/)
Design is the process of producing an implementation from a conceptual form
## [Chip Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/definitions/chip-design-and-verification/)
The design, verification, implementation and test of electronics systems into integrated circuits.
## [Chip Thermal Interface Protocol](https://semiengineering.com/knowledge_centers/low-power/techniques/chip-thermal-interface-protocol/)
Exchange of thermal design information for 3D ICs
## [Chiplet Fundamentals For Engineers: 2026 eBook](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/chiplets/chiplets-deep-dive-into-designing-manufacturing-and-testing/)
## [Chiplets](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/chiplets/)
A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.
There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.
With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.
A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.
Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandouâs chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandouâs interconnect technology.
DARPAâs approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.
The CHIPS program started in 2017. The program has various types of contractors/sub-contractorsâmanufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).
## [Clock Domain Crossing (CDC)](https://semiengineering.com/knowledge_centers/eda-design/verification/clock-domain-crossing/)
Asynchronous communications across boundaries
## [Clock Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/clock-gating-2/)
Dynamic power reduction by gating the clock
## [Clock Tree Optimization](https://semiengineering.com/knowledge_centers/low-power/techniques/clock-tree-optimization/)
Design of clock trees for power reduction
## [CMOS](https://semiengineering.com/knowledge_centers/materials/cmos/)
Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.
CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.
## [Co-Packaged Optics](https://semiengineering.com/knowledge_centers/data-movement/photonics/co-packaged-optics/)
## [Code Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/code-coverage/)
Metrics related to about of code executed in functional verification
## [Combinatorial Equivalence Checking](https://semiengineering.com/knowledge_centers/eda-design/definitions/combinatorial-equivalence-checking/)
Verify functionality between registers remains unchanged after a transformation
## [Companies & Organizations](https://semiengineering.com/knowledge_centers/entities/)
## [Compiled-code Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/compiled-code-simulation/)
Faster form for logic simulation
## [Complementary FET (CFET)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/cfet/)
Complementary FET, a new type of vertical transistor.
## [Compound Semiconductors](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/)
Combinations of semiconductor materials.
## [Compute Express Link (CXL)](https://semiengineering.com/knowledge_centers/standards-laws/standards/compute-express-link-cxl/)
Interconnect between CPU and accelerators.
## [Contact](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/contact/)
The structure that connects a transistor with the first layer of copper interconnects.
## [Convolutional Neural Network (CNN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/convolutional-neural-network/)
A technique for computer vision based on machine learning.
## [Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/)
Completion metrics for functional verification
## [Crosstalk](https://semiengineering.com/knowledge_centers/eda-design/noise-2/crosstalk/)
Interference between signals
## [Crypto processors](https://semiengineering.com/knowledge_centers/semiconductor-security/crypto-processors/)
Crypto processors are specialized processors that execute cryptographic algorithms within hardware.
## [Dark Silicon](https://semiengineering.com/knowledge_centers/low-power/techniques/dark-silicon/)
A method of conserving power in ICs by powering down segments of a chip when they are not in use.
## [Data Analytics](https://semiengineering.com/knowledge_centers/test/data-analytics/)
Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.
## [Data Analytics & Test](https://semiengineering.com/knowledge_centers/test/)
How semiconductors are sorted and tested before and after implementation of the chip in a system.
## [Data Movement](https://semiengineering.com/knowledge_centers/data-movement/)
The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.
## [Debug](https://semiengineering.com/knowledge_centers/eda-design/verification/debug/)
The removal of bugs from a design
## [Deep Learning (DL)](https://semiengineering.com/knowledge_centers/artificial-intelligence/machine-learning/deep-learning/)
Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.
## [Definitions](https://semiengineering.com/knowledge_centers/eda-design/definitions/)
## [Dennardâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/dennards-law/)
An observation that as features shrink, so does power consumption.
## [Deposition](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/)
## [Design for Manufacturing (DFM)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/design-for-manufacturing-dfm/)
Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.
## [Design for Test (DFT)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/design-for-test-dft/)
Techniques that reduce the difficulty and cost associated with testing an integrated circuit.
## [Design Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/design-patent/)
Protection for the ornamental design of an item
## [Design Rule Checking (DRC)](https://semiengineering.com/knowledge_centers/eda-design/verification/design-rule-checking-drc/)
A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer
## [Design Rule Pattern Matching](https://semiengineering.com/knowledge_centers/eda-design/verification/design-rule-pattern-matching/)
Locating design rules using pattern matching techniques.
## [Device Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/device-noise/)
Sources of noise in devices
## [DFT and Clock Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/dft-and-clock-gating/)
Insertion of test logic for clock-gating
## [Diamond Semiconductors](https://semiengineering.com/knowledge_centers/materials/diamond-semiconductors/)
A wide-bandgap synthetic material.
## [Digital IP](https://semiengineering.com/knowledge_centers/intellectual-property/digital-ip/)
Categorization of digital IP
## [Digital Oscilloscope](https://semiengineering.com/knowledge_centers/test/digital-oscilloscope/)
Allowed an image to be saved digitally
## [Digital Signal Processor (DSP)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/digital-signal-processor-dsp/)
A digital signal processor is a processor optimized to process signals.
## [Digital Twins](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/digital-twins/)
A digital representation of a product or system.
## [Directed Self-Assembly (DSA)](https://semiengineering.com/knowledge_centers/manufacturing/process/directed-self-assembly/)
A complementary lithography technology.
## [DNA biometrics](https://semiengineering.com/knowledge_centers/semiconductor-security/biometrics/dna-biometrics/)
DNA analysis is based upon unique DNA sequencing.
## [Domain/Distributed Architecture](https://semiengineering.com/knowledge_centers/automotive/domain-distributed-architecture/)
## [Double Data Rate (DDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/dynamic-random-access-memory/double-data-rate-ddr/)
## [Double Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/)
A patterning technique using multiple passes of a laser.
## [Double Patterning Methodologies](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/double-patterning-methodologies/)
Colored and colorless flows for double patterning
## [DRAM: Dynamic Random Access Memory](https://semiengineering.com/knowledge_centers/memory/volatile-memory/dynamic-random-access-memory/)
Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.
Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.
In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.
DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.
Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.
The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.
Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these
The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.
## [Dynamic Voltage and Frequency Scaling (DVFS)](https://semiengineering.com/knowledge_centers/low-power/techniques/dynamic-voltage-and-frequency-scaling/)
Dynamically adjusting voltage and frequency for power reduction
## [e](https://semiengineering.com/knowledge_centers/languages/e/)
Hardware Verification Language
## [E-beam Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/e-beam-inspection/)
A slower method for finding smaller defects.
## [E-Beam Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/ebeam/)
Lithography using a single beam e-beam tool
## [EBooks by Semiconductor Engineering](https://semiengineering.com/knowledge_centers/ebooks-by-semiconductor-engineering/)
## [EDA & Design](https://semiengineering.com/knowledge_centers/eda-design/)
## [Edge AI](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/)
## [Edge Computing](https://semiengineering.com/knowledge_centers/edge-computing/)
## [Edge Placement Error (EPE)](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/edge-placement-error/)
The difference between the intended and the printed features of an IC layout.
## [Electromigration](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/electromigration/)
Electromigration (EM) due to power densities
## [Electronic Design Automation (EDA)](https://semiengineering.com/knowledge_centers/eda-design/definitions/electronic-design-automation/)
Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.
## [Electronic System Level (ESL)](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/electronic-system-level/)
Levels of abstraction higher than RTL used for design and verification
## [Electrostatic Discharge (ESD)](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/electrostatic-discharge-esd/)
Transfer of electrostatic charge.
## [Embedded FPGA (eFPGA)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/fpga/embedded-fpga-efpga/)
An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.
## [Emulation](https://semiengineering.com/knowledge_centers/eda-design/verification/emulation/)
Special purpose hardware used for logic verification
## [Energy Harvesting](https://semiengineering.com/knowledge_centers/low-power/techniques/energy-harvesting/)
Capturing energy from the environment
## [Engineers: Jobs & Education](https://semiengineering.com/knowledge_centers/engineering-jobs-education/)
## [Environmental Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/environmental-noise/)
Noise caused by the environment
## [Epitaxy](https://semiengineering.com/knowledge_centers/manufacturing/process/epitaxy/)
A method for growing or depositing mono crystalline films on a substrate.
## [eRM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/erm/)
Reuse methodology based on the e language
## [**Error Correction Code (ECC)** (where you are)](https://semiengineering.com/knowledge_centers/memory/error-correction-code-ecc/)
Methods for detecting and correcting errors.
## [Ethernet](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/ethernet/)
Ethernet is a reliable, open standard for connecting devices by wire.
## [EUV: Extreme Ultraviolet Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/euv/)
EUV lithography is a soft X-ray technology.
## [Failure Analysis](https://semiengineering.com/knowledge_centers/manufacturing/process/failure-analysis/)
Finding out what went wrong in semiconductor design and manufacturing.
## [Fan-Outs](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/fan-outs/)
A way of including more features that normally would be on a printed circuit board inside a package.
## [Fault Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/fault-simulation/)
Evaluation of a design under the presence of manufacturing defects
## [Ferroelectric FETs (FeFET)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/fefets/)
Ferroelectric FET is a new type of memory.
## [Field Programmable Gate Array (FPGA)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/fpga/)
Reprogrammable logic device
## [FinFET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/finfet-3/)
A three-dimensional transistor.
## [Flash Memory](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/flash-memory/)
Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.
The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.
Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.
With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.
## [Flexible Hybrid Electronics (FHE)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/flexible-hybrid-electronics-fhe/)
Integrated circuits on a flexible substrate
## [FlexRay ISO 17458](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/flexray/)
An automotive communications protocol
## [Flicker Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/flicker-noise/)
Noise related to resistance fluctuation
## [Flip-Chip](https://semiengineering.com/knowledge_centers/packaging/flip-chip/)
A type of interconnect using solder balls or microbumps.
## [Forksheet FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/forksheet-fet/)
A transistor type with integrated nFET and pFET.
## [Formal Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/formal-verification/)
Formal verification involves a mathematical proof to show that a design adheres to a property
## [Foundry, pure-play foundry](https://semiengineering.com/knowledge_centers/manufacturing/foundry-pure-play-foundry/)
A company that specializes in manufacturing semiconductor devices.
## [Functional Coverage](https://semiengineering.com/knowledge_centers/eda-design/verification/coverage/functional-coverage/)
Coverage metric used to indicate progress in verifying functionality
## [Functional Design and Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/functional-design-and-verification/)
Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.
## [Functional Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/functional-verification/)
Functional verification is used to determine if a design, or unit of a design, conforms to its specification.
## [Gage R\&R, Gage Repeatability And Reproducibility](https://semiengineering.com/knowledge_centers/test/gage-rr-gage-repeatability-and-reproducibility/)
A statistical method for determining if a test system is production ready by measuring variation during test for repeatability and reproducibility.
## [Gallium Nitride (GaN)](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/gallium-nitride/)
GaN is a III-V material with a wide bandgap.
## [Gate-All-Around FET (GAA FET)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/gate-all-around-fet/)
A transistor design with a gate is placed on all four sides of the channel.
## [Gate-Level Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/gate-level-power-optimizations/)
Power reduction techniques available at the gate level.
## [Generation-Recombination Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/generation-recombination-noise/)
noise related to generation-recombination
## [Generative Adversarial Network (GAN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/generative-adversarial-network-gan/)
A neural network framework that can generate new data.
## [Germany](https://semiengineering.com/knowledge_centers/regional-developments-issues/germany/)
Germany is known for its automotive industry and industrial machinery.
## [Graphene](https://semiengineering.com/knowledge_centers/materials/2d-materials/graphene/)
Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.
The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.
Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2â
Vâ1â
sâ1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.
While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.
## [Graphics Double Data Rate (GDDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/graphics-double-data-rate-gddr/)
## [Graphics Processing Unit (GPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/graphics-processing-unit-gpu/)
An electronic circuit designed to handle graphics and video.
## [Guard Banding](https://semiengineering.com/knowledge_centers/eda-design/definitions/guard-banding/)
Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.
## [Hard IP](https://semiengineering.com/knowledge_centers/intellectual-property/hard-ip/)
Fully designed hardware IP block
## [Hardware Assisted Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/hardware-assisted-verification/)
Use of special purpose hardware to accelerate verification
## [Hardware Modeler](https://semiengineering.com/knowledge_centers/eda-design/models/hardware-modeler/)
Historical solution that used real chips in the simulation process
## [hardware/software co-design](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hardware-software-co-design/)
Optimizing the design by using a single language to describe hardware and software.
## [Heat Dissipation](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/heat-dissipation/)
Power creates heat and heat affects power
## [Heterogeneous Integration](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/heterogeneous-integration/)
The process of integrating different chips, chiplets, and chip components into packages.
## [High-Bandwidth Memory (HBM)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/high-bandwidth-memory/)
A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.
## [High-Density Advanced Packaging (HDAP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/high-density-advanced-packaging-hdap/)
An umbrella term (circa 2015) for advanced packaging in semiconductors.
## [High-Level Synthesis (HLS)](https://semiengineering.com/knowledge_centers/eda-design/verification/high-level-synthesis/)
Synthesis technology that transforms an untimed behavioral description into RTL
## [HSA Platform System Architecture Specification](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hsa-platform-system-architecture-specification/)
Defines a set of functionality and features for HSA hardware
## [HSA Runtime Programmerâs Reference Manual](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/hsa-runtime-programmeraes-reference-manual/)
Runtime capabilities for the HSA architecture
## [Hybrid Bonding](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/hybrid-bonding/)
## [IC Types](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/)
What are the types of integrated circuits?
## [IEEE 1076-VHSIC HW Description Language](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076/)
Hardware Description Language
## [IEEE 1076.1-Analog & Mixed-Signal](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-1/)
Analog extensions to VHDL
## [IEEE 1076.1.1-VHDL-AMS Standard Packages](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-1-1/)
A collection of VHDL 1076.1 packages
## [IEEE 1076.4-VHDL Synthesis Package â Floating Point](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1076-4/)
Modeling of macro-cells in VHDL
## [IEEE 1149 Boundary Scan Test](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1149/)
Boundry Scan Test
## [IEEE 1364-Verilog](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1364/)
IEEE ratified version of Verilog
## [IEEE 1364.1-Verilog RTL Synthesis](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1364-1/)
Standard for Verilog Register Transfer Level Synthesis
## [IEEE 1532- in-system programmability (ISP)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1532/)
Extension to 1149.1 for complex device programming
## [IEEE 1647-Functional Verification Language e](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1647/)
Functional verification language
## [IEEE 1666-Standard SystemC](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1666/)
SystemC
## [IEEE 1685-IP-XACT](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1685/)
Standard for integration of IP in System-on-Chip
## [IEEE 1687-IEEE Standard for Access and Control of Instrumentation Embedded](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1687/)
IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
## [IEEE 1800-SystemVerilog](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1800/)
IEEE ratified version of SystemVerilog
## [IEEE 1800.2âUVM](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1800-2/)
Universal Verification Methodology
## [IEEE 1801-Design/Verification of Low-Power, Energy-Aware UPF](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1801/)
IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)
## [IEEE 1838: Test Access Architecture for 3D Stacked IC](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1838/)
Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
## [IEEE 1850-Property Specification Language (PSL)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-1850/)
Verification language based on formal specification of behavior
## [IEEE 802.1-Higher Layer LAN Protocols](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-1-higher-layer-lan-protocols/)
IEEE 802.1 is the standard and working group for higher layer LAN protocols.
## [IEEE 802.11-Wireless LAN](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-11-wireless-lan/)
IEEE 802.11 working group manages the standards for wireless local area networks (LANs).
## [IEEE 802.15-Wireless Specialty Networks (WSN)](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-15-wireless-specialty-networks-wsn/)
IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.
## [IEEE 802.18-Radio Regulatory TAG](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-18-radio-regulatory/)
"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.
## [IEEE 802.19-Wireless Coexistence](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-19-wireless-coexistence/)
Standards for coexistence between wireless standards of unlicensed devices.
## [IEEE 802.3-Ethernet](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-802-3-ethernet/)
IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.
## [IEEE P2415: Unified HW Abstraction & Layer for Energy Proportional Electronic Systems](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-p2415/)
Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
## [IEEE P2416-Power Modeling](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-p2416/)
Power Modeling Standard for Enabling System Level Analysis
## [IEEE-ISTO 5001 (Nexus 5001) â embedded processor debug](https://semiengineering.com/knowledge_centers/standards-laws/standards/ieee-isto-5001-standard-nexus-5001/)
## [IIoT: Industrial Internet of Things](https://semiengineering.com/knowledge_centers/edge-computing/industrial-internet-of-things/)
Specific requirements and special consideration for the Internet of Things within an Industrial setting.
## [Impact of lithography on wafer costs](https://semiengineering.com/knowledge_centers/manufacturing/lithography/impact-of-lithography-on-wafer-costs/)
Wafer costs across nodes
## [Implementation Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/implementation-power-optimizations/)
Power optimization techniques for physical implementation
## [In-Memory Computing](https://semiengineering.com/knowledge_centers/compute-architectures/in-memory-computing/)
Performing functions directly in the fabric of memory.
## [Induced Gate Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/induced-gate-noise/)
Thermal noise within a channel
## [Insulated-Gate Bipolar Transistors (IGBT)](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/insulated-gate-bipolar-transistors/)
IGBTs are combinations of MOSFETs and bipolar transistors.
## [Integrated Circuits (ICs)](https://semiengineering.com/knowledge_centers/integrated-circuit/)
Integration of multiple devices onto a single piece of semiconductor
## [Integrated Device Manufacturer (IDM)](https://semiengineering.com/knowledge_centers/manufacturing/integrated-device-manufacturer-idm/)
A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).
## [Intellectual Property (IP)](https://semiengineering.com/knowledge_centers/intellectual-property/)
A design or verification unit that is pre-packed and available for licensing.
## [Inter Partes Review](https://semiengineering.com/knowledge_centers/standards-laws/patents/inter-partes-review/)
Method to ascertain the validity of one or more claims of a patent
## [Interconnects](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/)
## [Interconnects (BEOL)](https://semiengineering.com/knowledge_centers/manufacturing/process/beol/interconnect/)
Buses, NoCs and other forms of connection between various elements in an integrated circuit.
## [Internet of Things (IoT)](https://semiengineering.com/knowledge_centers/edge-computing/internet-of-things/)
Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.
## [Interposers](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/2-5d-ic/interposers/)
Fast, low-power inter-die conduits for 2.5D electrical signals.
## [Inverse Lithography Technology (ILT)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/inverse-lithography-technology-ilt/)
Finding ideal shapes to use on a photomask.
## [Ion Implants](https://semiengineering.com/knowledge_centers/manufacturing/process/ion-implants/)
Injection of critical dopants during the semiconductor manufacturing process.
## [IP-XACT](https://semiengineering.com/knowledge_centers/standards-laws/standards/ip-xact/)
Standard for integration of IP in System-on-Chip
## [IR Drop](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/ir-drop/)
The voltage drop when current flows through a resistor.
## [ISO 21434 / SAE 21434 Standard â Automotive cybersecurity](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-21434-sae-21434-standard-automotive-cybersecurity/)
## [ISO 26262 â Functional safety](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-26262/)
Standard related to the safety of electrical and electronic systems within a car
## [ISO/PAS 21448 â SOTIF](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/iso-pas-21448-sotif/)
Standard to ensure proper operation of automotive situational awareness systems.
## [ISO/SAE FDIS 21434-Road Vehicles â Cybersecurity Engineering](https://semiengineering.com/knowledge_centers/standards-laws/standards/iso-sae-fdis-21434-road-vehicles-cybersecurity-engineering/)
A standard (under development) for automotive cybersecurity.
## [Israel](https://semiengineering.com/knowledge_centers/regional-developments-issues/israel/)
## [Issues](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/)
## [Koomeyâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/koomeys-law/)
The energy efficiency of computers doubles roughly every 18 months.
## [Languages](https://semiengineering.com/knowledge_centers/languages/)
Languages are used to create models
## [Large Language Models (LLMs)](https://semiengineering.com/knowledge_centers/artificial-intelligence/large-language-models/)
## [Laws](https://semiengineering.com/knowledge_centers/standards-laws/laws/)
Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.
## [Layout versus Schematic Checking (LVS)](https://semiengineering.com/knowledge_centers/eda-design/definitions/layout-versus-schematic-checking/)
Device and connectivity comparisons between the layout and the schematic
## [Level Shifters](https://semiengineering.com/knowledge_centers/low-power/techniques/level-shifters-2/)
Cells used to match voltages across voltage islands
## [Line Edge Roughness (LER)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/line-edge-roughness-ler/)
Deviation of a feature edge from ideal shape.
## [Lint](https://semiengineering.com/knowledge_centers/eda-design/verification/lint/)
Removal of non-portable or suspicious code
## [Litho Etch Litho Etch (LELE)](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/litho-etch-litho-etch/)
LELE is a form of double patterning
## [Litho Freeze Litho Etch](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/litho-freeze-litho-etch/)
A type of double patterning.
## [Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/)
Light used to transfer a pattern from a photomask onto a substrate.
## [Lithography k1 coefficient](https://semiengineering.com/knowledge_centers/manufacturing/lithography/lithography-k1-coefficient/)
Coefficient related to the difficulty of the lithography process
## [Logic Resizing](https://semiengineering.com/knowledge_centers/eda-design/definitions/logic-resizing-2/)
Correctly sizing logic elements
## [Logic Restructuring](https://semiengineering.com/knowledge_centers/eda-design/definitions/logic-restructuring-2/)
Restructuring of logic for power reduction
## [Logic Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/)
A simulator is a software process used to execute a model of hardware
## [Low Power Double Data Rate (LPDDR)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/low-power-double-data-rate-lpddr/)
## [Low Power Methodologies](https://semiengineering.com/knowledge_centers/low-power/techniques/low-power-methodologies/)
Methodologies used to reduce power consumption.
## [Low Power Verification](https://semiengineering.com/knowledge_centers/low-power/low-power-verification/)
Verification of power circuitry
## [Low-Power Design](https://semiengineering.com/knowledge_centers/low-power/low-power-design/)
## [Machine Learning (ML)](https://semiengineering.com/knowledge_centers/artificial-intelligence/machine-learning/)
An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.
## [Magnetoresistive RAM (MRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/)
Uses magnetic properties to store data
## [Makimotoâs Wave](https://semiengineering.com/knowledge_centers/standards-laws/laws/makimotos-wave/)
Observation related to the amount of custom and standard content in electronics.
## [Manufacturing Execution System (MES)](https://semiengineering.com/knowledge_centers/manufacturing/manufacturing-execution-system-mes/)
Tracking a wafer through the fab.
## [Manufacturing Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/manufacturing-noise/)
Noise sources in manufacturing
## [Materials](https://semiengineering.com/knowledge_centers/materials/)
Semiconductor materials enable electronic circuits to be constructed.
## [Memory](https://semiengineering.com/knowledge_centers/memory/)
A semiconductor device capable of retaining state information for a defined period of time.
## [MEMS](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/analog-circuits/mems/)
Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.
## [Metal Organic Chemical Vapor Deposition (MOCVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/metal-organic-chemical-vapor-deposition/)
A key tool for LED production.
## [Metastability](https://semiengineering.com/knowledge_centers/eda-design/definitions/metastability/)
Unstable state within a latch
## [Metcalfeâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/metcalfeaes-law/)
Observation that relates network value being proportional to the square of users
## [Methodologies and Flows](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/)
Describes the process to create a product
## [Metrology](https://semiengineering.com/knowledge_centers/manufacturing/process/metrology/)
Metrology is the science of measuring and characterizing tiny structures and materials.
## [Microcontroller (MCU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/microcontroller-mcu/)
A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.
## [Microprocessor, Microprocessor Unit (MPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/microprocessor-microprocessor-unit-mpu/)
The integrated circuit that first put a central processing unit on one chip of silicon.
## [Mixed-Signal](https://semiengineering.com/knowledge_centers/eda-design/definitions/mixed-signal/)
The integration of analog and digital.
## [Models](https://semiengineering.com/knowledge_centers/eda-design/models/)
## [Models and Abstractions](https://semiengineering.com/knowledge_centers/eda-design/models/models-and-abstractions/)
Models are abstractions of devices
## [Molded Interconnect Substrate (MIS)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/molded-interconnect-substrate/)
A midrange packaging option that offers lower density than fan-outs.
## [Monolithic 3D Chips](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/3d-ics/monolithic-3d-chips/)
A way of stacking transistors inside a single chip instead of a package.
## [Mooreâs Law](https://semiengineering.com/knowledge_centers/standards-laws/laws/moores-law/)
Observation related to the growth of semiconductors by Gordon Moore.
## [Multi-Beam e-Beam Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/ebeam/multi-beam-ebeam-lithography/)
An advanced form of e-beam lithography
## [Multi-chip Modules (MCM)](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/multi-chip-modules/)
An early approach to bundling multiple functions into a single package.
## [Multi-Corner Multi-Mode (MCMM) Analysis](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/multi-corner-multi-mode-analysis/)
Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
## [Multi-Die Assemblies](https://semiengineering.com/knowledge_centers/packaging/multi-die-assemblies/)
## [Multi-site testing](https://semiengineering.com/knowledge_centers/test/multi-site-testing/)
Using a tester to test multiple dies at the same time.
## [Multi-Vt](https://semiengineering.com/knowledge_centers/low-power/techniques/multi-vt/)
Use of multi-threshold voltage devices
## [Multiple Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/multipatterning/)
A way to image IC designs at 20nm and below.
## [Nanoimprint Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/nanoimprint-lithography/)
A hot embossing process type of lithography.
## [Nanosheet FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/nanosheet-fet/)
A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.
## [Near Threshold Computing](https://semiengineering.com/knowledge_centers/low-power/techniques/near-threshold-computing/)
Optimizing power by computing below the minimum operating voltage.
## [Near-Memory Computing](https://semiengineering.com/knowledge_centers/compute-architectures/near-memory-computing/)
Moving compute closer to memory to reduce access costs.
## [Negative Bias Temperature Instability (NBTI)](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/negative-bias-temperature-instability/)
NBTI is a shift in threshold voltage with applied stress.
## [Network on Chip (NoC)](https://semiengineering.com/knowledge_centers/data-movement/network-on-chip-noc/)
An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.
## [Neural Networks](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/)
A method of collecting data from the physical world that mimics the human brain.
## [Neuromorphic Computing](https://semiengineering.com/knowledge_centers/compute-architectures/neuromorphic-computing/)
A compute architecture modeled on the human brain.
## [Nodes](https://semiengineering.com/knowledge_centers/manufacturing/process/nodes/)
Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.
## [Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/)
Random fluctuations in voltage or current on a signal.
## [Non-Volatile Memory (NVM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/)
Memory in which information is retained even when a power source is not present.
Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1
NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and whatâs being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.
Fundamentally, there are two types of NVM:
Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.
Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.
Then thereâs the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, itâs difficult to do it because the oxide thickness is not there to do to make it happen.
However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.
The OTP technology doesnât require the thicker oxide that is required for the MTP, and there is no floating gate.
1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/
## [Open Verification Methodology (OVM)](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/ovm/)
Verification methodology created from URM and AVM
## [Operand Isolation](https://semiengineering.com/knowledge_centers/low-power/techniques/operand-isolation-2/)
Disabling datapath computation when not enabled
## [Optical Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/optical-inspection/)
Method used to find defects on a wafer.
## [Optical Lithography](https://semiengineering.com/knowledge_centers/manufacturing/lithography/optical-lithography/)
## [Optical Proximity Correction (OPC)](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/optical-proximity-correction-opc/)
A way to improve wafer printability by modifying mask patterns.
## [Original Equipment Manufacturer (OEM)](https://semiengineering.com/knowledge_centers/manufacturing/original-equipment-manufacturer-oem/)
The company that buys raw goods, including electronics and chips, to make a product.
## [Outsourced Semiconductor Assembly and Test (OSAT)](https://semiengineering.com/knowledge_centers/packaging/outsourced-semiconductor-assembly-and-test/)
Companies who perform IC packaging and testing - often referred to as OSAT
## [Overlay](https://semiengineering.com/knowledge_centers/manufacturing/lithography/overlay/)
The ability of a lithography scanner to align and print various layers accurately on top of each other.
## [package-on-package (PoP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/package-on-package-pop/)
## [Packaging](https://semiengineering.com/knowledge_centers/packaging/)
How semiconductors get assembled and packaged.
## [Part Average Testing (PAT)](https://semiengineering.com/knowledge_centers/test/part-average-testing-pat/)
Outlier detection for a single measurement, a requirement for automotive electronics.
## [Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/)
## [PCI Express (PCIe), Peripheral Component Interconnect Express](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/pci-express-pcie-peripheral-component-interconnect-express/)
High-speed serial expansion bus for connecting sending data between devices.
## [Pellicle](https://semiengineering.com/knowledge_centers/manufacturing/lithography/pellicle/)
A thin membrane that prevents a photomask from being contaminated.
## [Phase-Change Memory](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/phase-change-memory/)
Memory that stores information in the amorphous and crystalline phases.
## [Photomask](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photomask/)
A template of what will be printed on a wafer.
## [Photonic Integrated Circuit (PIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/photonic-integrated-circuit-pic/)
## [Photonics](https://semiengineering.com/knowledge_centers/data-movement/photonics/)
## [Photoresist](https://semiengineering.com/knowledge_centers/manufacturing/lithography/photoresist/)
Light-sensitive material used to form a pattern on the substrate.
## [Physical AI](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/physical-ai/)
## [Physical Design](https://semiengineering.com/knowledge_centers/eda-design/definitions/physical-design/)
Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.
## [Physical Layer (PHY)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/phy/)
Physically connects devices and is the conduit that encodes, decodes bits of data.
## [Physical Vapor Deposition (PVD)](https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/physical-vapor-deposition/)
PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.
## [Physical Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/physical-verification/)
Making sure a design layout works as intended.
## [Physically Unclonable Functions (PUFs)](https://semiengineering.com/knowledge_centers/semiconductor-security/physically-unclonable-functions/)
A set of unique features that can be built into a chip but not cloned.
## [Pin Swapping](https://semiengineering.com/knowledge_centers/low-power/techniques/pin-swapping-2/)
Lowering capacitive loads on logic
## [Planar](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/)
## [PODEM](https://semiengineering.com/knowledge_centers/test/automatic-test-pattern-generation/podem/)
An algorithm used ATPG
## [Portable Stimulus (PSS)](https://semiengineering.com/knowledge_centers/languages/portable_stimulus/)
Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.
## [Power](https://semiengineering.com/knowledge_centers/low-power/)
## [Power Consumption](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-consumption/)
Components of power consumption
## [Power Cycle Sequencing](https://semiengineering.com/knowledge_centers/low-power/techniques/power-cycle-sequencing/)
Power domain shutdown and startup
## [Power Definitions](https://semiengineering.com/knowledge_centers/low-power/power-definitions/)
Definitions of terms related to power
## [Power Delivery Network (PDN)](https://semiengineering.com/knowledge_centers/low-power/power-delivery-network-pdn/)
Moving power around a device.
## [Power Estimation](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-estimation/)
How is power consumption estimated
## [Power Gating](https://semiengineering.com/knowledge_centers/low-power/techniques/power-gating/)
Reducing power by turning off parts of a design
## [Power Gating Retention](https://semiengineering.com/knowledge_centers/low-power/techniques/power-gating/power-gating-retention/)
Special flop or latch used to retain the state of the cell when its main power supply is shut off.
## [Power Isolation](https://semiengineering.com/knowledge_centers/low-power/techniques/power-isolation/)
Addition of isolation cells around power islands
## [Power Issues](https://semiengineering.com/knowledge_centers/low-power/architectural-power-issues/)
Power reduction at the architectural level
## [Power Management Coverage](https://semiengineering.com/knowledge_centers/low-power/power-management-coverage/)
Ensuring power control circuitry is fully verified
## [Power Management IC (PMIC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-management-ic-pmic/)
An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.
## [Power MOSFETs](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/planar/power-mosfets/)
A power semiconductor used to control and convert electric power.
## [Power Semiconductors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-semiconductors-power-ic/)
A power IC is used as a switch or rectifier in high voltage power applications.
## [Power Semiconductors Report: A Deep Dive Into Materials, Manufacturing & Business](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/power-semiconductors-power-ic/power-semiconductors-report-a-deep-dive-into-materials-manufacturing-business/)
## [Power Supply Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/power-supply-noise/)
Noise transmitted through the power delivery network
## [Power Switching](https://semiengineering.com/knowledge_centers/low-power/techniques/power-switching/)
Controlling power for power shutoff
## [Power Techniques](https://semiengineering.com/knowledge_centers/low-power/techniques/)
## [Power-Aware Design](https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-aware-design/)
Techniques that analyze and optimize power in a design
## [Power-Aware Test](https://semiengineering.com/knowledge_centers/test/power-aware-test-2/)
Test considerations for low-power circuitry
## [PPA (Power, Performance, Area)](https://semiengineering.com/knowledge_centers/eda-design/definitions/ppa/)
Fundamental tradeoffs made in semiconductor design for power, performance and area.
## [Printed Circuit Board (PCB)](https://semiengineering.com/knowledge_centers/eda-design/definitions/printed-circuit-board/)
The design, verification, assembly and test of printed circuit boards
## [Process](https://semiengineering.com/knowledge_centers/manufacturing/process/)
## [Process Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/process-power-optimizations/)
power optimization techniques at the process level
## [Process Variation](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/variability/)
Variability in the semiconductor manufacturing process
## [Processor Utilization](https://semiengineering.com/knowledge_centers/eda-design/verification/processor-utilization/)
A measurement of the amount of time processor core(s) are actively in use.
## [Processors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/)
An integrated circuit or part of an IC that does logic and math processing.
## [Property Specification Language](https://semiengineering.com/knowledge_centers/languages/property-specification-language/)
Verification language based on formal specification of behavior
## [Quantum Computing](https://semiengineering.com/knowledge_centers/compute-architectures/quantum-computing/)
A different way of processing data using qubits.
## [Radio Frequency (RF)](https://semiengineering.com/knowledge_centers/data-movement/wireless/rf/)
Issues that pertain to Radio Frequency (RF) analog
## [Random Telegraph Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/random-telegraph-noise/)
Random trapping of charge carriers
## [Rapid Thermal Anneal (RTA), Rapid Thermal Processing (RTP)](https://semiengineering.com/knowledge_centers/manufacturing/process/rapid-thermal-anneal-rta-rapid-thermal-processing-rtp/)
The process of rapidly heating wafers.
## [Redistribution Layers (RDLs)](https://semiengineering.com/knowledge_centers/packaging/redistribution-layers-rdls/)
Copper metal interconnects that electrically connect one part of a package to another.
## [Regional Developments/Issues](https://semiengineering.com/knowledge_centers/regional-developments-issues/)
## [Reliability Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/reliability-verification/)
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.
## [ReRAM materials](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/resistive-ram/reram-materials/)
Materials used to manufacture ReRAMs
## [Resistive RAM (ReRAM/RRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/resistive-ram/)
Memory utilizing resistive hysteresis
## [Reticle](https://semiengineering.com/knowledge_centers/manufacturing/lithography/reticle/)
Synonymous with photomask.
## [Rich Interactive Test Database (RITdb)](https://semiengineering.com/knowledge_centers/test/data-analytics/rich-interactive-test-database-ritdb/)
A proposed test data standard aimed at reducing the burden for test engineers and test operations.
## [RISC-V](https://semiengineering.com/knowledge_centers/compute-architectures/risc-v/)
An open-source ISA used in designing integrated circuits at lower cost.
## [Root of Trust](https://semiengineering.com/knowledge_centers/semiconductor-security/root-of-trust/)
Trusted environment for secure functions.
## [RTL (Register Transfer Level)](https://semiengineering.com/knowledge_centers/eda-design/definitions/register-transfer-level/)
An abstraction for defining the digital portions of a design
## [RTL Power Optimizations](https://semiengineering.com/knowledge_centers/low-power/techniques/rtl-power-optimizations/)
Optimization of power consumption at the Register Transfer Level
## [RTL Signoff](https://semiengineering.com/knowledge_centers/eda-design/verification/rtl-signoff/)
A series of requirements that must be met before moving past the RTL phase
## [RVM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/rvm/)
Verification methodology based on Vera
## [SAT Solver](https://semiengineering.com/knowledge_centers/eda-design/verification/sat-solver/)
Algorithm used to solve problems
## [Scan Test](https://semiengineering.com/knowledge_centers/test/scan-test-2/)
Additional logic that connects registers into a shift register or scan chain for increased test efficiency.
## [Scoreboard](https://semiengineering.com/knowledge_centers/eda-design/verification/scoreboard/)
Mechanism for storing stimulus in testbench
## [SCV SystemC Verification](https://semiengineering.com/knowledge_centers/standards-laws/standards/scv/)
Testbench support for SystemC
## [Self-Aligned Double Patterning (SADP)](https://semiengineering.com/knowledge_centers/manufacturing/patterning/double-patterning/self-aligned-double-patterning/)
A form of double patterning.
## [Semiconductor Manufacturing](https://semiengineering.com/knowledge_centers/manufacturing/)
Subjects related to the manufacture of semiconductors
## [Semiconductor Security](https://semiengineering.com/knowledge_centers/semiconductor-security/)
Methods and technologies for keeping data safe.
## [Sensor Fusion](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/sensor-fusion/)
Combining input from multiple sensor types.
## [Sensor Signal Conditioner (SSC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/sensor-signal-conditioner-ssc/)
An IC that conditions an analog sensor signal and converts to it digital before sending to a microcontroller.
## [Sensors](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/sensors/)
Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.
## [serializer/deserializer (SerDes)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/serializer-deserializer-serdes/)
A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.
## [Shift Left](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/shift-left/)
In semiconductor development flow, tasks once performed sequentially must now be done concurrently.
## [Shmooing, Shmoo test, Shmoo plot](https://semiengineering.com/knowledge_centers/test/shmooing-shmoo-test-shmoo-plot/)
Sweeping a test condition parameter through a range and obtaining a plot of the results.
## [Short Channel Effects](https://semiengineering.com/knowledge_centers/manufacturing/process/issues/short-channel-effects/)
When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.
## [Shot Noise](https://semiengineering.com/knowledge_centers/manufacturing/lithography/shot-noise/)
Quantization noise
## [Side Channel Attacks](https://semiengineering.com/knowledge_centers/semiconductor-security/side-channel-attacks/)
A class of attacks on a device and its contents by analyzing information using different access methods.
## [Silent Data Corruption (SDC)](https://semiengineering.com/knowledge_centers/test/silent-data-corruption-sdc/)
Undetected errors in data output from an integrated circuit.
## [Silicon Carbide (SiC)](https://semiengineering.com/knowledge_centers/materials/compound-semiconductors/silicon-carbide/)
A wide-bandgap technology used for FETs and MOSFETs for power transistors.
## [Silicon Photonics](https://semiengineering.com/knowledge_centers/data-movement/photonics/silicon-photonics/)
The integration of photonic devices into silicon
## [Simulation](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/)
A simulator exercises of model of hardware
## [Simulation Acceleration](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/simulation-acceleration/)
Special purpose hardware used to accelerate the simulation process.
## [Simultaneous Switching Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/simultaneous-switching-noise/)
Disturbance in ground voltage
## [Small Language Models (SLMs)](https://semiengineering.com/knowledge_centers/artificial-intelligence/edge-ai/small-language-models-slms/)
## [Soft IP](https://semiengineering.com/knowledge_centers/intellectual-property/soft-ip/)
Synthesizable IP block
## [Software-Defined Vehicles (SDV)](https://semiengineering.com/knowledge_centers/automotive/software-defined-vehicles/)
## [Software-Driven Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/software-driven-verification/)
Verification methodology utilizing embedded processors
## [Software/Hardware Interface for Multicore/Manycore (SHIM) processors](https://semiengineering.com/knowledge_centers/eda-design/methodologies-and-flows/softwarehardware-interface-for-multicoremanycore-shim-processors/)
Defines an architecture description useful for software design
## [SPICE](https://semiengineering.com/knowledge_centers/eda-design/verification/simulation/spice/)
Circuit Simulator first developed in the 70s
## [Spiking Neural Network (SNN)](https://semiengineering.com/knowledge_centers/artificial-intelligence/neural-networks/spiking-neural-network-snn/)
A type of neural network that attempts to more closely model the brain.
## [Spin-Orbit Torque MRAM (SOT-MRAM)](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/spin-orbit-torque-mram-sot-mram/)
A type of MRAM with separate paths for write and read.
## [Standard Essential Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/standard-essential-patent/)
A patent that has been deemed necessary to implement a standard.
## [Standard Test Data Format (STDF)](https://semiengineering.com/knowledge_centers/test/data-analytics/standard-test-data-format-stdf/)
The most commonly used data format for semiconductor test information.
## [Standards](https://semiengineering.com/knowledge_centers/standards-laws/standards/)
Standards are important in any industry.
## [Standards & Laws](https://semiengineering.com/knowledge_centers/standards-laws/)
## [Startup Funding in China eBook: Notable investments in the semiconductor industry](https://semiengineering.com/knowledge_centers/regional-developments-issues/china/startup-funding-in-china-2022-ebook/)
## [Startups](https://semiengineering.com/knowledge_centers/startups/)
## [Static Random Access Memory (SRAM)](https://semiengineering.com/knowledge_centers/memory/volatile-memory/static-random-access-memory/)
SRAM is a volatile memory that does not require refresh
## [Stimulus Constraints](https://semiengineering.com/knowledge_centers/eda-design/verification/stimulus-constraints/)
Constraints on the input to guide random generation process
## [Stochastics, Stochastic-Induced Defects](https://semiengineering.com/knowledge_centers/manufacturing/lithography/euv/stochastics-stochastic-induced-defects/)
Random variables that cause defects on chips during EUV lithography.
## [STT-MRAM](https://semiengineering.com/knowledge_centers/memory/non-volatile-memory-nvm/magnetoresistive-ram/stt-mram/)
An advanced type of MRAM
## [Substrate Biasing](https://semiengineering.com/knowledge_centers/low-power/techniques/substrate-biasing/)
Use of Substrate Biasing
## [Substrate Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/substrate-noise/)
Coupling through the substrate.
## [System In Package (SiP)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/system-in-package/)
A method for bundling multiple ICs to work together as a single chip.
## [System on Chip (SoC)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/system-on-chip/)
A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor
## [SystemC](https://semiengineering.com/knowledge_centers/languages/systemc/)
A class library built on top of the C++ language used for modeling hardware
## [SystemC-AMS](https://semiengineering.com/knowledge_centers/languages/systemc-ams/)
Analog and mixed-signal extensions to SystemC
## [SystemVerilog](https://semiengineering.com/knowledge_centers/languages/systemverilog/)
Industry standard design and verification language
## [Tensor Processing Unit (TPU)](https://semiengineering.com/knowledge_centers/integrated-circuit/ic-types/processors/tensor-processing-unit-tpu/)
Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.
## [Testbench](https://semiengineering.com/knowledge_centers/eda-design/verification/testbench/)
Software used to functionally verify a design
## [Thermal Noise](https://semiengineering.com/knowledge_centers/eda-design/noise-2/thermal-noise/)
Noise related to heat
## [Through-Silicon Vias (TSVs)](https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/through-silicon-vias/)
Through-Silicon Vias are a technology to connect various die in a stacked die configuration.
## [Trace](https://semiengineering.com/knowledge_centers/test/trace/)
## [Transistors](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/)
Basic building block for both analog and digital integrated circuits.
## [Transition Rate Buffering](https://semiengineering.com/knowledge_centers/low-power/techniques/transition-rate-buffering-2/)
Minimizing switching times
## [Triple Patterning](https://semiengineering.com/knowledge_centers/manufacturing/patterning/triple-patterning/)
A multi-patterning technique that will be required at 10nm and below.
## [Tunnel FET](https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/tunnel-fet/)
A type of transistor under development that could replace finFETs in future process technologies.
## [UL 4600 â Standard for Safety for the Evaluation of Autonomous Products](https://semiengineering.com/knowledge_centers/automotive/automotive-standards/ul-4600-standard-for-safety-for-the-evaluation-of-autonomous-products/)
Standard for safety analysis and evaluation of autonomous vehicles.
## [Unified Coverage Interoperability Standard (Verification)](https://semiengineering.com/knowledge_centers/standards-laws/standards/unified-coverage-interoperability-standard/)
The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.
## [Unified Power Format (UPF)](https://semiengineering.com/knowledge_centers/standards-laws/standards/unified-power-format/)
Accellera Unified Power Format (UPF)
## [Universal Chiplet Interconnect Express (UCIe)](https://semiengineering.com/knowledge_centers/data-movement/on-chip-communications/universal-chiplet-interconnect-express-ucie/)
Die-to-die interconnect specification.
## [Universal Verification Methodology (UVM)](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/uvm/)
Verification methodology
## [URM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/urm/)
SystemVerilog version of eRM
## [User Interfaces](https://semiengineering.com/knowledge_centers/user-interfaces/)
User interfaces is the conduit a human uses to communicate with an electronics device.
## [Utility Patent](https://semiengineering.com/knowledge_centers/standards-laws/patents/utility-patent/)
Patent to protect an invention
## [Vera](https://semiengineering.com/knowledge_centers/languages/vera/)
Hardware Verification Language
## [Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/)
## [Verification IP (VIP)](https://semiengineering.com/knowledge_centers/intellectual-property/verification-ip-vip/)
A pre-packaged set of code used for verification.
## [Verification Methodologies](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/)
A standardized way to verify integrated circuit designs.
## [Verification Plan](https://semiengineering.com/knowledge_centers/eda-design/verification/verification-plan/)
A document that defines what functional verification is going to be performed
## [Verilog](https://semiengineering.com/knowledge_centers/languages/verilog/)
Hardware Description Language in use since 1984
## [Verilog Procedural Interface](https://semiengineering.com/knowledge_centers/languages/verilog/verilog-procedural-interface/)
Procedural access to Verilog objects
## [Verilog-AMS](https://semiengineering.com/knowledge_centers/standards-laws/standards/verilog-ams/)
Analog extensions to Verilog
## [VHDL](https://semiengineering.com/knowledge_centers/languages/vhdl/)
Hardware Description Language
## [Virtual Prototype](https://semiengineering.com/knowledge_centers/eda-design/verification/virtual-prototype/)
An abstract model of a hardware system enabling early software execution.
## [VMM](https://semiengineering.com/knowledge_centers/eda-design/verification/methodology/vmm/)
Verification methodology built by Synopsys
## [Voice control, speech recognition, voice-user interface (VUI)](https://semiengineering.com/knowledge_centers/user-interfaces/voice-control-speech-recognition-voice-user-interface-vui/)
Using voice/speech for device command and control.
## [Volatile Memory](https://semiengineering.com/knowledge_centers/memory/volatile-memory/)
Memory that loses storage abilities when power is removed.
## [Voltage Islands](https://semiengineering.com/knowledge_centers/low-power/techniques/voltage-islands/)
Use of multiple voltages for power reduction
## [Von Neumann Architecture](https://semiengineering.com/knowledge_centers/compute-architectures/von-neumann-architecture/)
The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.
## [Wafer Fab Testing](https://semiengineering.com/knowledge_centers/test/wafer-fab-testing/)
Verifying and testing the dies on the wafer after the manufacturing.
## [Wafer Inspection](https://semiengineering.com/knowledge_centers/manufacturing/process/wafer-inspection/)
The science of finding defects on a silicon wafer.
## [Wi-Fi](https://semiengineering.com/knowledge_centers/data-movement/wireless/wi-fi/)
A brand name for a group of wireless networking protocols and technology,
## [Wide I/O: memory interface standard for 3D IC](https://semiengineering.com/knowledge_centers/standards-laws/standards/wide-io-2/)
3D memory interface standard
## [Wirebonding](https://semiengineering.com/knowledge_centers/packaging/wirebonding/)
Creating interconnects between IC and package using a thin wire.
## [Wireless](https://semiengineering.com/knowledge_centers/data-movement/wireless/)
A way of moving data without wires.
## [X Architecture](https://semiengineering.com/knowledge_centers/low-power/techniques/x-architecture/)
IC interconnect architecture
## [X Verification](https://semiengineering.com/knowledge_centers/eda-design/verification/x-verification/)
X Propagation causes problems
## [Yield Management System (YMS)](https://semiengineering.com/knowledge_centers/manufacturing/yield-management-system-yms/)
A data-driven system for monitoring and improving IC yield and reliability.
## [Zero-Day Vulnerabilities, Attacks](https://semiengineering.com/knowledge_centers/semiconductor-security/zero-day-vulnerabilities-attacks/)
A vulnerability in a productâs hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.
## [Zonal Architectures](https://semiengineering.com/knowledge_centers/automotive/zonal-architectures/)
## [Aart de Geus](https://semiengineering.com/people/aart-de-geus/)
## [Adam Kablanian](https://semiengineering.com/people/adam-kablanian/)
## [Aditya Mittal](https://semiengineering.com/people/aditya-mittal/)
## [Adnan Hamid](https://semiengineering.com/people/adnan-hamid/)
## [Adrian Simionescu](https://semiengineering.com/people/adrian-simionescu/)
## [Ahmed Hemani](https://semiengineering.com/people/ahmed-hemani/)
## [Ajay Daga](https://semiengineering.com/people/ajay-daga/)
## [Ajoy K. Bose](https://semiengineering.com/people/ajoy-k-bose/)
## [Akash Deshpande](https://semiengineering.com/people/akash-deshpande/)
## [Aki Fujimura](https://semiengineering.com/people/aki-fujimura/)
## [Al Akermann](https://semiengineering.com/people/al-akermann/)
## [Alain Fanet](https://semiengineering.com/people/alain-fanet/)
## [Alain J. Hanover](https://semiengineering.com/people/alain-j-hanover/)
## [Alakesh Chetia](https://semiengineering.com/people/alakesh-chetia/)
## [Alan Scott](https://semiengineering.com/people/alan-scott/)
## [Alberto Sangiovanni-Vincentelli](https://semiengineering.com/people/alberto-sangiovanni-vincentelli/)
## [Alex Alexanian](https://semiengineering.com/people/alex-alexanian/)
## [Alexander Samoylov](https://semiengineering.com/people/alexander-samoylov/)
## [Alisa Yaffa](https://semiengineering.com/people/alisa-yaffa/)
## [Allan Douglas](https://semiengineering.com/people/allan-douglas/)
## [Amir Zarkesh](https://semiengineering.com/people/amir-zarkesh/)
## [Amit Gupta](https://semiengineering.com/people/amit-gupta/)
## [Amit Mehrotra](https://semiengineering.com/people/amit-mehrotra/)
## [Amit Narayan](https://semiengineering.com/people/amit-narayan/)
## [Amit Saxena](https://semiengineering.com/people/amit-saxena/)
## [Amr Mohsen](https://semiengineering.com/people/amr-mohsen/)
## [An-Chang Deng](https://semiengineering.com/people/an-chang-deng/)
## [An-Yu Kuo](https://semiengineering.com/people/an-yu-kuo/)
## [Anant Agarwal](https://semiengineering.com/people/anant-agarwal/)
## [AndrĂĄs Poppe](https://semiengineering.com/people/andras-poppe/)
## [Andrea Casotto](https://semiengineering.com/people/andrea-casotto/)
## [Andreas Ripp](https://semiengineering.com/people/andreas-ripp/)
## [Andreas Veneris](https://semiengineering.com/people/andreas-veneris/)
## [Andrei Tcherniaev](https://semiengineering.com/people/andrei-tcherniaev/)
## [Andrew Hughes](https://semiengineering.com/people/andrew-hughes/)
## [Andrew T. Yang](https://semiengineering.com/people/andrew-t-yang/)
## [Andrzej Strojwas](https://semiengineering.com/people/andrzej-strojwas/)
## [Andy Chou](https://semiengineering.com/people/andy-chou/)
## [Andy Goodrich](https://semiengineering.com/people/andy-goodrich/)
## [Andy Huang](https://semiengineering.com/people/andy-huang/)
## [Andy Ladd](https://semiengineering.com/people/andy-ladd/)
## [Andy Lin](https://semiengineering.com/people/andy-lin/)
## [Ange Aznar](https://semiengineering.com/people/ange-aznar/)
## [Anmol Mathur](https://semiengineering.com/people/anmol-mathur/)
## [Anupam Bakshi](https://semiengineering.com/people/anupam-bakshi/)
## [Apo Sezginer](https://semiengineering.com/people/apo-sezginer/)
## [Apostolos Liapist](https://semiengineering.com/people/apostolos-liapist/)
## [Aram Mirkazemi](https://semiengineering.com/people/aram-mirkazemi/)
## [Ari Takanen](https://semiengineering.com/people/ari-takanen/)
## [Armin Biere](https://semiengineering.com/people/armin-biere/)
## [Arnaud Schleich](https://semiengineering.com/people/arnaud-schleich/)
## [Arul Sharan](https://semiengineering.com/people/arul-sharan/)
## [Arvind Mithal](https://semiengineering.com/people/arvind-mithal/)
## [Aryeh Finegold](https://semiengineering.com/people/aryeh-finegold/)
## [Asen Asenov](https://semiengineering.com/people/asen-asenov/)
## [Ashawna Hailey](https://semiengineering.com/people/ashawna-hailey/)
## [Ashraf Takla](https://semiengineering.com/people/ashraf-takla/)
## [Asoke K. Laha](https://semiengineering.com/people/asoke-k-laha/)
## [Atsushi Kasuya](https://semiengineering.com/people/atsushi-kasuya/)
## [Atul Bhagat](https://semiengineering.com/people/atul-bhagat/)
## [Atul Bhatia](https://semiengineering.com/people/atul-bhatia/)
## [Aurangzeb Khan](https://semiengineering.com/people/aurangzeb-khan/)
## [Avideh Zakhor](https://semiengineering.com/people/avideh-zakhor/)
## [Avishai Silvershatz](https://semiengineering.com/people/avishai-silvershatz/)
## [Axel Jantsch](https://semiengineering.com/people/axel-jantsch/)
## [Babu Chilukuri](https://semiengineering.com/people/babu-chilukuri/)
## [Badru Agarwala](https://semiengineering.com/people/badru-agarwala/)
## [Barry Katz](https://semiengineering.com/people/barry-katz/)
## [Barry Rosales](https://semiengineering.com/people/barry-rosales/)
## [Bart De Smedt](https://semiengineering.com/people/bart-de-smedt/)
## [Becky Cavanaugh](https://semiengineering.com/people/becky-cavanaugh/)
## [Ben Chelf](https://semiengineering.com/people/ben-chelf/)
## [Ben Levine](https://semiengineering.com/people/ben-levine/)
## [Bendt Sorensen](https://semiengineering.com/people/bendt-sorensen/)
## [Bernard Vonderschmitt](https://semiengineering.com/people/bernard-vonderschmitt/)
## [Bernie Rosenthal](https://semiengineering.com/people/bernie-rosenthal/)
## [Bill Berg](https://semiengineering.com/people/bill-berg/)
## [Bill Buckie](https://semiengineering.com/people/bill-buckie/)
## [Bill Childs](https://semiengineering.com/people/bill-childs/)
## [Bill Hoover](https://semiengineering.com/people/bill-hoover/)
## [Bill Krieger](https://semiengineering.com/people/bill-krieger/)
## [Bill Neifert](https://semiengineering.com/people/bill-neifert/)
## [Bill Robertson](https://semiengineering.com/people/bill-robertson/)
## [Bill Sommer](https://semiengineering.com/people/bill-sommer/)
## [Biman Chattopadhyay](https://semiengineering.com/people/biman-chattopadhyay/)
## [Bing Yeh](https://semiengineering.com/people/bing-yeh/)
## [Bob Flatt](https://semiengineering.com/people/bob-flatt/)
## [Bob Hunter](https://semiengineering.com/people/bob-hunter/)
## [Bob Quinn](https://semiengineering.com/people/bob-quinn/)
## [Borgar Ljosland](https://semiengineering.com/people/borgar-ljosland/)
## [Boris Gruzman](https://semiengineering.com/people/boris-gruzman/)
## [Brad Quinton](https://semiengineering.com/people/brad-quinton/)
## [Brian Davenpoort](https://semiengineering.com/people/brian-davenpoort/)
## [Bruce M. Holland](https://semiengineering.com/people/bruce-m-holland/)
## [Bryan Hoyer](https://semiengineering.com/people/bryan-hoyer/)
## [Carson Bradbury](https://semiengineering.com/people/carson-bradbury/)
## [Carver Mead](https://semiengineering.com/people/carver-mead/)
## [CĂŠsar Douady](https://semiengineering.com/people/casar-douady/)
## [Char Devich](https://semiengineering.com/people/char-devich/)
## [Charles Edelstenne](https://semiengineering.com/people/charles-edelstenne/)
## [Charles Evans](https://semiengineering.com/people/charles-evans/)
## [Charles J. (Chuck) Abronson](https://semiengineering.com/people/charles-j-chuck-abronson/)
## [Charlie Cheng](https://semiengineering.com/people/charlie-cheng/)
## [Charlie Huang](https://semiengineering.com/people/charlie-huang/)
## [Cheng Wang](https://semiengineering.com/people/cheng-wang/)
## [Chenming Hu](https://semiengineering.com/people/chenming-hu/)
## [Chi-Lai Huang](https://semiengineering.com/people/chi-lai-huang/)
## [Ching-Chao Huang](https://semiengineering.com/people/ching-chao-huang/)
## [Chioumin (Michael) Chang](https://semiengineering.com/people/chioumin-michael-chang/)
## [Chong Ming (Frank) Lin](https://semiengineering.com/people/chong-ming-frank-lin/)
## [Chouki Aktouf](https://semiengineering.com/people/chouki-aktouf/)
## [Chris Schalick](https://semiengineering.com/people/chris-schalick/)
## [Chris Wilson](https://semiengineering.com/people/chris-wilson/)
## [Chris Curry](https://semiengineering.com/people/chris-curry/)
## [Chris Rosebrugh](https://semiengineering.com/people/chris-rosebrugh/)
## [Chris Rowen](https://semiengineering.com/people/chris-rowen/)
## [Christian Masson](https://semiengineering.com/people/christian-masson/)
## [Christophe Alexandre](https://semiengineering.com/people/christophe-alexandre/)
## [Chung-Kuan Cheng](https://semiengineering.com/people/chung-kuan-cheng/)
## [Claes StrannegĂĽrd](https://semiengineering.com/people/claes-strannega%C2%A5rd/)
## [Claudio Basile](https://semiengineering.com/people/claudio-basile/)
## [Cleve Moler](https://semiengineering.com/people/cleve-moler/)
## [Clifton (Cliff) Lyons](https://semiengineering.com/people/clifton-cliff-lyons/)
## [Clinton W. Kelly](https://semiengineering.com/people/clinton-w-kelly/)
## [Coby Zelnik](https://semiengineering.com/people/coby-zelnik/)
## [Colin Hunter](https://semiengineering.com/people/colin-hunter/)
## [Craig Harris](https://semiengineering.com/people/craig-harris/)
## [Craig Honegger](https://semiengineering.com/people/craig-honegger/)
## [Craig Gleason](https://semiengineering.com/people/craig-gleason/)
## [Craig Stoops](https://semiengineering.com/people/craig-stoops/)
## [Cristian Amitroaie](https://semiengineering.com/people/cristian-amitroaie/)
## [Cyril Spasevski](https://semiengineering.com/people/cyril-spasevski/)
## [Cyrus Afghahi](https://semiengineering.com/people/cyrus-afghahi/)
## [Da Chuang](https://semiengineering.com/people/da-chuang/)
## [Damian Smith](https://semiengineering.com/people/damian-smith/)
## [Dan Abrams](https://semiengineering.com/people/dan-abrams/)
## [Dan Chapiro](https://semiengineering.com/people/dan-chapiro/)
## [Dan Jaskolski](https://semiengineering.com/people/dan-jaskolski/)
## [Dan Malek](https://semiengineering.com/people/dan-malek/)
## [Danesh Tavana](https://semiengineering.com/people/danesh-tavana/)
## [Daniel Hansson](https://semiengineering.com/people/daniel-hansson/)
## [Dave Gregory](https://semiengineering.com/people/dave-gregory/)
## [Dave Millman](https://semiengineering.com/people/dave-millman/)
## [Dave Moffenbeier](https://semiengineering.com/people/dave-moffenbeier/)
## [David Marple](https://semiengineering.com/people/david-marple/)
## [David Botting](https://semiengineering.com/people/david-botting/)
## [David Chyan](https://semiengineering.com/people/david-chyan/)
## [David Coelho](https://semiengineering.com/people/david-coelho/)
## [David E. Long](https://semiengineering.com/people/david-e-long/)
## [David Galloway](https://semiengineering.com/people/david-galloway/)
## [David Greaves](https://semiengineering.com/people/david-greaves/)
## [David Hamilton](https://semiengineering.com/people/david-hamilton/)
## [David Henke](https://semiengineering.com/people/david-henke/)
## [David Johannsen](https://semiengineering.com/people/david-johannsen/)
## [David Novosel](https://semiengineering.com/people/david-novosel/)
## [David Overhauser](https://semiengineering.com/people/david-overhauser/)
## [David Park](https://semiengineering.com/people/david-park/)
## [David Pellerin](https://semiengineering.com/people/david-pellerin/)
## [David R. Stevens](https://semiengineering.com/people/david-r-stevens/)
## [David Stamm](https://semiengineering.com/people/david-stamm/)
## [David Stewart](https://semiengineering.com/people/david-stewart/)
## [David Yao](https://semiengineering.com/people/david-yao/)
## [Davorin Mista](https://semiengineering.com/people/davorin-mista/)
## [Dawson Engler](https://semiengineering.com/people/dawson-engler/)
## [Dean Drako](https://semiengineering.com/people/dean-drako/)
## [Deepak Shankar](https://semiengineering.com/people/deepak-shankar/)
## [Deepak Kumar Tala](https://semiengineering.com/people/deepak-kumar-tala/)
## [Dejan Markovic](https://semiengineering.com/people/dejan-markovic/)
## [Derek King](https://semiengineering.com/people/derek-king/)
## [Devadas Varma](https://semiengineering.com/people/devadas-varma/)
## [Devesh Guatam](https://semiengineering.com/people/devesh-guatam/)
## [Diana Marculescu](https://semiengineering.com/people/diana-marculescu/)
## [Dirk Lanneer](https://semiengineering.com/people/dirk-lanneer/)
## [Dominik Strasser](https://semiengineering.com/people/dominik-strasser/)
## [Don Emil Pezzolo](https://semiengineering.com/people/don-emil-pezzolo/)
## [Don McInnis](https://semiengineering.com/people/don-mcinnis/)
## [Don-Min Tsou](https://semiengineering.com/people/don-min-tsou/)
## [Donald Bennett](https://semiengineering.com/people/donald-bennett/)
## [Doug Fairbairn](https://semiengineering.com/people/doug-fairbairn/)
## [Drew E. Wingard](https://semiengineering.com/people/drew-e-wingard/)
## [Duncan Bremner](https://semiengineering.com/people/duncan-bremner/)
## [Durga Lakshmi Sangisetti](https://semiengineering.com/people/durga-lakshmi-sangisetti/)
## [Ed Blackmond](https://semiengineering.com/people/ed-blackmond/)
## [Edmund K. Cheng](https://semiengineering.com/people/edmund-k-cheng/)
## [Edvard Sørgürd](https://semiengineering.com/people/edvard-sa%C2%B8rga%C2%A5rd/)
## [Edward A. Lee](https://semiengineering.com/people/edward-a-lee/)
## [Edward Komp](https://semiengineering.com/people/edward-komp/)
## [Edward N. Evans](https://semiengineering.com/people/edward-n-evans/)
## [Egino Sarto](https://semiengineering.com/people/egino-sarto/)
## [Elena Potanina](https://semiengineering.com/people/elena-potanina/)
## [Eli Yablonovitch](https://semiengineering.com/people/eli-yablonovitch/)
## [Ellis Smith](https://semiengineering.com/people/ellis-smith/)
## [Enno Wein](https://semiengineering.com/people/enno-wein/)
## [Eric Ryherd](https://semiengineering.com/people/eric-ryherd/)
## [Eric Beisser](https://semiengineering.com/people/eric-beisser/)
## [Eric Dormer](https://semiengineering.com/people/eric-dormer/)
## [Eric Dupont](https://semiengineering.com/people/eric-dupont/)
## [Eric Dupont-Nivet](https://semiengineering.com/people/eric-dupont-nivet/)
## [Eric Peers](https://semiengineering.com/people/eric-peers/)
## [Eric T. Hennenhoefer](https://semiengineering.com/people/eric-t-hennenhoefer/)
## [Erik Lauwers](https://semiengineering.com/people/erik-lauwers/)
## [Esin Terzioglu](https://semiengineering.com/people/esin-terzioglu/)
## [Eun Sei Park](https://semiengineering.com/people/eun-sei-park/)
## [Ewald Detjens](https://semiengineering.com/people/ewald-detjens/)
## [Fadil Kotaji](https://semiengineering.com/people/fadil-kotaji/)
## [Fang-Cheng Chang](https://semiengineering.com/people/fang-cheng-chang/)
## [Fang-Li Yuan](https://semiengineering.com/people/fang-li-yuan/)
## [Farakh Javid](https://semiengineering.com/people/farakh-javid/)
## [Fergus Slorach](https://semiengineering.com/people/fergus-slorach/)
## [Fia Johansson](https://semiengineering.com/people/fia-johansson/)
## [Firas Mohamed](https://semiengineering.com/people/firas-mohamed/)
## [Founder(s) Unknown](https://semiengineering.com/people/founders-unknown/)
## [François Constant](https://semiengineering.com/people/frana%C2%A7ois-constant/)
## [Francis Bernard](https://semiengineering.com/people/francis-bernard/)
## [Frank Gennari](https://semiengineering.com/people/frank-gennari/)
## [Frank Costa](https://semiengineering.com/people/frank-costa/)
## [Frank DeRemer](https://semiengineering.com/people/frank-deremer/)
## [Frank Schenkel](https://semiengineering.com/people/frank-schenkel/)
## [Franz Dugand](https://semiengineering.com/people/franz-dugand/)
## [Frederic Reblewski](https://semiengineering.com/people/frederic-reblewski/)
## [Frederick (Fred) Saal](https://semiengineering.com/people/frederick-fred-saal/)
## [Fuad Musa](https://semiengineering.com/people/fuad-musa/)
## [Fumiaki Sato](https://semiengineering.com/people/fumiaki-sato/)
## [Gabi Leshem](https://semiengineering.com/people/gabi-leshem/)
## [Gagan Hasteer](https://semiengineering.com/people/gagan-hasteer/)
## [Ganapathy Subramaniam](https://semiengineering.com/people/ganapathy-subramaniam/)
## [Gene Dancause](https://semiengineering.com/people/gene-dancause/)
## [Gene Marsh](https://semiengineering.com/people/gene-marsh/)
## [Geoffrey Tate](https://semiengineering.com/people/geoffrey-tate/)
## [Gerald H. Langeler](https://semiengineering.com/people/gerald-h-langeler/)
## [Gerald L (Jerry) Frenkil](https://semiengineering.com/people/gerald-l-jerry-frenkil/)
## [Gerald Pechanek](https://semiengineering.com/people/gerald-pechanek/)
## [Gerhard Angst](https://semiengineering.com/people/gerhard-angst/)
## [Gert Goossens](https://semiengineering.com/people/gert-goossens/)
## [Ghassan (Gus) Y. Yacoub](https://semiengineering.com/people/ghassan-gus-y-yacoub/)
## [Ghislain Kaiser](https://semiengineering.com/people/ghislain-kaiser/)
## [Giacinto Paolo Saggese](https://semiengineering.com/people/giacinto-paolo-saggese/)
## [Gil Winograd](https://semiengineering.com/people/gil-winograd/)
## [Glen M. Antle](https://semiengineering.com/people/glen-m-antle/)
## [Gopa Periyadan](https://semiengineering.com/people/gopa-periyadan/)
## [Gopal Krishna Nayak](https://semiengineering.com/people/gopal-krishna-nayak/)
## [Gordon B. Hoffman](https://semiengineering.com/people/gordon-b-hoffman/)
## [Gordon Baty](https://semiengineering.com/people/gordon-baty/)
## [Gordon E. Moore](https://semiengineering.com/people/gordon-e-moore/)
## [Graham Hellestrand](https://semiengineering.com/people/graham-hellestrand/)
## [Grant A. Pierce](https://semiengineering.com/people/grant-a-pierce/)
## [Greg Doyle](https://semiengineering.com/people/greg-doyle/)
## [Greg Hoeppner](https://semiengineering.com/people/greg-hoeppner/)
## [Greg Lloyd](https://semiengineering.com/people/greg-lloyd/)
## [Greg M. Ordy](https://semiengineering.com/people/greg-m-ordy/)
## [Gregory Recupero](https://semiengineering.com/people/gregory-recupero/)
## [Guido Arnout](https://semiengineering.com/people/guido-arnout/)
## [GĂźnter Keil](https://semiengineering.com/people/ga%C2%BCnter-keil/)
## [Guy Bois](https://semiengineering.com/people/guy-bois/)
## [Guy de Burgh](https://semiengineering.com/people/guy-de-burgh/)
## [Hal Alles](https://semiengineering.com/people/hal-alles/)
## [Hal Conklin](https://semiengineering.com/people/hal-conklin/)
## [Hamid Savoj](https://semiengineering.com/people/hamid-savoj/)
## [Harald Neubauer](https://semiengineering.com/people/harald-neubauer/)
## [Hardeep Gulati](https://semiengineering.com/people/hardeep-gulati/)
## [Harm Arts](https://semiengineering.com/people/harm-arts/)
## [HarnHua Ng](https://semiengineering.com/people/harnhua-ng/)
## [Harvey C. Jones jr.](https://semiengineering.com/people/harvey-c-jones-jr/)
## [Hayder Mrabet](https://semiengineering.com/people/hayder-mrabet/)
## [Hazem El Tahawy](https://semiengineering.com/people/hazem-el-tahawy/)
## [Hein van der Wildt](https://semiengineering.com/people/hein-van-der-wildt/)
## [Heinrich Meyr](https://semiengineering.com/people/heinrich-meyr/)
## [Helmut Gräb](https://semiengineering.com/people/helmut-gra%C2%A4b/)
## [Helmut Mahr](https://semiengineering.com/people/helmut-mahr/)
## [Henrik Pallisgaard](https://semiengineering.com/people/henrik-pallisgaard/)
## [Henry Cox](https://semiengineering.com/people/henry-cox/)
## [Hermann Hauser](https://semiengineering.com/people/hermann-hauser/)
## [Hiro Moriyasu](https://semiengineering.com/people/hiro-moriyasu/)
## [Holly Stump](https://semiengineering.com/people/holly-stump/)
## [Howard L. Martin](https://semiengineering.com/people/howard-l-martin/)
## [Howard Pakosh](https://semiengineering.com/people/howard-pakosh/)
## [Ian Lankshear](https://semiengineering.com/people/ian-lankshear/)
## [Ian Page](https://semiengineering.com/people/ian-page/)
## [Ian Tsybulkin](https://semiengineering.com/people/ian-tsybulkin/)
## [Ihao Chen](https://semiengineering.com/people/ihao-chen/)
## [Ivan Pesic](https://semiengineering.com/people/ivan-pesic/)
## [J. Eric Bracken](https://semiengineering.com/people/j-eric-bracken/)
## [J. George Janac](https://semiengineering.com/people/j-george-janac/)
## [Jack Herrick](https://semiengineering.com/people/jack-herrick/)
## [Jack Harding](https://semiengineering.com/people/jack-harding/)
## [Jack Little](https://semiengineering.com/people/jack-little/)
## [Jack Peng](https://semiengineering.com/people/jack-peng/)
## [Jacob Ben-Meir](https://semiengineering.com/people/jacob-ben-meir/)
## [James (Jim) Fiske](https://semiengineering.com/people/james-jim-fiske/)
## [James (Jim) Ready](https://semiengineering.com/people/james-jim-ready/)
## [James B. Morris](https://semiengineering.com/people/james-b-morris/)
## [James C. Rautio](https://semiengineering.com/people/james-c-rautio/)
## [James E. (Jim) Solomon](https://semiengineering.com/people/james-e-jim-solomon/)
## [James G. Crocker](https://semiengineering.com/people/james-g-crocker/)
## [James Girand](https://semiengineering.com/people/james-girand/)
## [James Truchard](https://semiengineering.com/people/james-truchard/)
## [James V Barnett II](https://semiengineering.com/people/james-v-barnett-ii/)
## [Jamsheed Agahi](https://semiengineering.com/people/jamsheed-agahi/)
## [Janak H. Patel](https://semiengineering.com/people/janak-h-patel/)
## [Jane Karwoski McCracken](https://semiengineering.com/people/jane-karwoski-mccracken/)
## [Jason Campbell](https://semiengineering.com/people/jason-campbell/)
## [Jason Cong](https://semiengineering.com/people/jason-cong/)
## [Jason Xing](https://semiengineering.com/people/jason-xing/)
## [Jauher Zaidi](https://semiengineering.com/people/jauher-zaidi/)
## [Jaushin Lee](https://semiengineering.com/people/jaushin-lee/)
## [Jay Avula](https://semiengineering.com/people/jay-avula/)
## [Jean Barbier](https://semiengineering.com/people/jean-barbier/)
## [Jean Brouwers](https://semiengineering.com/people/jean-brouwers/)
## [Jean-Luc Pelloie](https://semiengineering.com/people/jean-luc-pelloie/)
## [Jean-Philippe Lambert](https://semiengineering.com/people/jean-philippe-lambert/)
## [Jean-Pierre Appel](https://semiengineering.com/people/jean-pierre-appel/)
## [Jean-Pierre Lecailliez](https://semiengineering.com/people/jean-pierre-lecailliez/)
## [Jean-Yves Brena](https://semiengineering.com/people/jean-yves-brena/)
## [Jeff Fox](https://semiengineering.com/people/jeff-fox/)
## [Jeff Bier](https://semiengineering.com/people/jeff-bier/)
## [Jeff Galloway](https://semiengineering.com/people/jeff-galloway/)
## [Jeff Kodosky](https://semiengineering.com/people/jeff-kodosky/)
## [Jeff Tuan](https://semiengineering.com/people/jeff-tuan/)
## [Jens C. Michelsen](https://semiengineering.com/people/jens-c-michelsen/)
## [Jens J. Tybo Jensen](https://semiengineering.com/people/jens-j-tybo-jensen/)
## [Jens P. Tagore-Brage](https://semiengineering.com/people/jens-p-tagore-brage/)
## [Jeong-Tyng Li](https://semiengineering.com/people/jeong-tyng-li/)
## [Jeremy Birch](https://semiengineering.com/people/jeremy-birch/)
## [Jerome Vanthournout](https://semiengineering.com/people/jerome-vanthournout/)
## [Jesper Knudsen](https://semiengineering.com/people/jesper-knudsen/)
## [Jez San](https://semiengineering.com/people/jez-san/)
## [Jian X. Zheng](https://semiengineering.com/people/jian-x-zheng/)
## [Jim McCanny](https://semiengineering.com/people/jim-mccanny/)
## [Jim Sansbury](https://semiengineering.com/people/jim-sansbury/)
## [Jinsong Zhao](https://semiengineering.com/people/jinsong-zhao/)
## [Joe Higgins](https://semiengineering.com/people/joe-higgins/)
## [Joe Tanous](https://semiengineering.com/people/joe-tanous/)
## [Joe Tatham](https://semiengineering.com/people/joe-tatham/)
## [Joerg Grosse](https://semiengineering.com/people/joerg-grosse/)
## [Joey Y. Lin](https://semiengineering.com/people/joey-y-lin/)
## [Johan Van Praet](https://semiengineering.com/people/johan-van-praet/)
## [Johan Peeters](https://semiengineering.com/people/johan-peeters/)
## [Johann Foucher](https://semiengineering.com/people/johann-foucher/)
## [Johannes Emigholz](https://semiengineering.com/people/johannes-emigholz/)
## [John Gilbert](https://semiengineering.com/people/john-gilbert/)
## [John A. Swanson](https://semiengineering.com/people/john-a-swanson/)
## [John Charles Carveth](https://semiengineering.com/people/john-charles-carveth/)
## [John Croix](https://semiengineering.com/people/john-croix/)
## [John Durbetaki](https://semiengineering.com/people/john-durbetaki/)
## [John F. Cooper](https://semiengineering.com/people/john-f-cooper/)
## [John Goodenough](https://semiengineering.com/people/john-goodenough/)
## [John Halfpenny](https://semiengineering.com/people/john-halfpenny/)
## [John Hall](https://semiengineering.com/people/john-hall/)
## [John Hatfield](https://semiengineering.com/people/john-hatfield/)
## [john Judkins](https://semiengineering.com/people/john-judkins/)
## [John K. Kibarian](https://semiengineering.com/people/john-k-kibarian/)
## [John Lee](https://semiengineering.com/people/john-lee/)
## [John Lofton Holt](https://semiengineering.com/people/john-lofton-holt/)
## [John Maneatis](https://semiengineering.com/people/john-maneatis/)
## [John Mills](https://semiengineering.com/people/john-mills/)
## [John Ott](https://semiengineering.com/people/john-ott/)
## [John R. Maticich](https://semiengineering.com/people/john-r-maticich/)
## [John Sanguinetti](https://semiengineering.com/people/john-sanguinetti/)
## [John Tanner](https://semiengineering.com/people/john-tanner/)
## [Johnathan Weiss](https://semiengineering.com/people/johnathan-weiss/)
## [Johnson Limqueco](https://semiengineering.com/people/johnson-limqueco/)
## [Jonathan Cagan](https://semiengineering.com/people/jonathan-cagan/)
## [Jonathan Rose](https://semiengineering.com/people/jonathan-rose/)
## [Jordan Swartz](https://semiengineering.com/people/jordan-swartz/)
## [Joseph Skazinski](https://semiengineering.com/people/joseph-skazinski/)
## [Joseph B. Costello](https://semiengineering.com/people/joseph-b-costello/)
## [Joseph E. Pekarek](https://semiengineering.com/people/joseph-e-pekarek/)
## [Joseph Lee](https://semiengineering.com/people/joseph-lee/)
## [Joseph Rothman](https://semiengineering.com/people/joseph-rothman/)
## [Josh Lee](https://semiengineering.com/people/josh-lee/)
## [Juliusz Poltz](https://semiengineering.com/people/juliusz-poltz/)
## [Jun-Jyeh Hsiao](https://semiengineering.com/people/jun-jyeh-hsiao/)
## [Jørn Nystad](https://semiengineering.com/people/ja%C2%B8rn-nystad/)
## [K. Charles Janac](https://semiengineering.com/people/k-charles-janac/)
## [K.C. Shih](https://semiengineering.com/people/k-c-shih/)
## [Kaiwin Lee](https://semiengineering.com/people/kaiwin-lee/)
## [Kamran Elahian](https://semiengineering.com/people/kamran-elahian/)
## [Kannankote Sriram](https://semiengineering.com/people/kannankote-sriram/)
## [Karel Masarik](https://semiengineering.com/people/karel-masarik/)
## [Karen Vahtra](https://semiengineering.com/people/karen-vahtra/)
## [Kaushik I. Sheth](https://semiengineering.com/people/kaushik-i-sheth/)
## [Kavitha Tala](https://semiengineering.com/people/kavitha-tala/)
## [Keith Short](https://semiengineering.com/people/keith-short/)
## [Keith Seymour](https://semiengineering.com/people/keith-seymour/)
## [Keith Whisnant](https://semiengineering.com/people/keith-whisnant/)
## [Ken McElvain](https://semiengineering.com/people/ken-mcelvain/)
## [Ken Matusow](https://semiengineering.com/people/ken-matusow/)
## [Ken Seymour](https://semiengineering.com/people/ken-seymour/)
## [Ken Tseng](https://semiengineering.com/people/ken-tseng/)
## [Kenneth L. Shepard](https://semiengineering.com/people/kenneth-l-shepard/)
## [Kevin Chou](https://semiengineering.com/people/kevin-chou/)
## [Kevin Hotaling](https://semiengineering.com/people/kevin-hotaling/)
## [Kevin Ladd](https://semiengineering.com/people/kevin-ladd/)
## [Khalil Shalish](https://semiengineering.com/people/khalil-shalish/)
## [Kim Hailey](https://semiengineering.com/people/kim-hailey/)
## [Kimon Michaels](https://semiengineering.com/people/kimon-michaels/)
## [Kirvy Teo](https://semiengineering.com/people/kirvy-teo/)
## [Kurt Matis](https://semiengineering.com/people/kurt-matis/)
## [L. Curtis Widdoes Jr.](https://semiengineering.com/people/l-curtis-widdoes-jr/)
## [L. John Doerr III](https://semiengineering.com/people/l-john-doerr-iii/)
## [L. Richard Carley](https://semiengineering.com/people/l-richard-carley/)
## [Larry Carver](https://semiengineering.com/people/larry-carver/)
## [Larry Lewis](https://semiengineering.com/people/larry-lewis/)
## [Larry Rubin](https://semiengineering.com/people/larry-rubin/)
## [Lars-Eric Lundgren](https://semiengineering.com/people/lars-eric-lundgren/)
## [Laurent Moss](https://semiengineering.com/people/laurent-moss/)
## [Laurent RougĂŠ](https://semiengineering.com/people/laurent-rouga/)
## [Lawrence T. (Larry) Pileggi](https://semiengineering.com/people/lawrence-t-larry-pileggi/)
## [Lee Tavrow](https://semiengineering.com/people/lee-tavrow/)
## [Lei He](https://semiengineering.com/people/lei-he/)
## [Lev A. Markov](https://semiengineering.com/people/lev-a-markov/)
## [Limin He](https://semiengineering.com/people/limin-he/)
## [Lip-Bu Tan](https://semiengineering.com/people/lip-bu-tan/)
## [Lisa McIlrath](https://semiengineering.com/people/lisa-mcilrath/)
## [Lloyd Pople](https://semiengineering.com/people/lloyd-pople/)
## [Lothar Linhard](https://semiengineering.com/people/lothar-linhard/)
## [Luc Burgun](https://semiengineering.com/people/luc-burgun/)
## [Lucio Lanza](https://semiengineering.com/people/lucio-lanza/)
## [Lukas van Ginneken](https://semiengineering.com/people/lukas-van-ginneken/)
## [Lutz P. Henckles](https://semiengineering.com/people/lutz-p-henckles/)
## [Maha Zaidi](https://semiengineering.com/people/maha-zaidi/)
## [Maheen Hamid](https://semiengineering.com/people/maheen-hamid/)
## [Mahesh Rao](https://semiengineering.com/people/mahesh-rao/)
## [Mahshad Koohgoli](https://semiengineering.com/people/mahshad-koohgoli/)
## [Manny Marcano](https://semiengineering.com/people/manny-marcano/)
## [Mar Hershenson](https://semiengineering.com/people/mar-hershenson/)
## [Marc Renaudin](https://semiengineering.com/people/marc-renaudin/)
## [Marc Witteman](https://semiengineering.com/people/marc-witteman/)
## [Marcelino Santos](https://semiengineering.com/people/marcelino-santos/)
## [Marco Rubinstein](https://semiengineering.com/people/marco-rubinstein/)
## [Margarida Sousa](https://semiengineering.com/people/margarida-sousa/)
## [Margie Levine](https://semiengineering.com/people/margie-levine/)
## [Mario Blazevic](https://semiengineering.com/people/mario-blazevic/)
## [Mark Beardslee](https://semiengineering.com/people/mark-beardslee/)
## [Mark Cianfaglione](https://semiengineering.com/people/mark-cianfaglione/)
## [Mark Hampton](https://semiengineering.com/people/mark-hampton/)
## [Mark Horowitz](https://semiengineering.com/people/mark-horowitz/)
## [Mark OâDonovan](https://semiengineering.com/people/mark-odonovan/)
## [Mark Olen](https://semiengineering.com/people/mark-olen/)
## [Mark R. Templeton](https://semiengineering.com/people/mark-r-templeton/)
## [Mark Santoro](https://semiengineering.com/people/mark-santoro/)
## [Mark Waller](https://semiengineering.com/people/mark-waller/)
## [Mark Williams](https://semiengineering.com/people/mark-williams/)
## [Mark-Eric Jones](https://semiengineering.com/people/mark-eric-jones/)
## [Markus Mergens](https://semiengineering.com/people/markus-mergens/)
## [Marleen Boonen](https://semiengineering.com/people/marleen-boonen/)
## [Martin Baechtold](https://semiengineering.com/people/martin-baechtold/)
## [Martin Langhammer](https://semiengineering.com/people/martin-langhammer/)
## [Martin Lefebvre](https://semiengineering.com/people/martin-lefebvre/)
## [Martin Walker](https://semiengineering.com/people/martin-walker/)
## [Martin Wilson](https://semiengineering.com/people/martin-wilson/)
## [Mathias Silvant](https://semiengineering.com/people/mathias-silvant/)
## [Maurice Whelan](https://semiengineering.com/people/maurice-whelan/)
## [Maurizio Arienzo](https://semiengineering.com/people/maurizio-arienzo/)
## [Maximilian Odendahl](https://semiengineering.com/people/maximilian-odendahl/)
## [Mehmet A. Cirit](https://semiengineering.com/people/mehmet-a-cirit/)
## [Mel Gilmore](https://semiengineering.com/people/mel-gilmore/)
## [Michael McNamara](https://semiengineering.com/people/michael-mcnamara/)
## [Michael Alam](https://semiengineering.com/people/michael-alam/)
## [Michael Burstein](https://semiengineering.com/people/michael-burstein/)
## [Michael D. Hoyt](https://semiengineering.com/people/michael-d-hoyt/)
## [Michael Goldstone](https://semiengineering.com/people/michael-goldstone/)
## [Michael J. Jamiolkowski](https://semiengineering.com/people/michael-j-jamiolkowski/)
## [Michael Magranet](https://semiengineering.com/people/michael-magranet/)
## [Michael Nicolaidis](https://semiengineering.com/people/michael-nicolaidis/)
## [Michael Pronath](https://semiengineering.com/people/michael-pronath/)
## [Michael Wakim](https://semiengineering.com/people/michael-wakim/)
## [Michel Oger](https://semiengineering.com/people/michel-oger/)
## [Mike Rieger](https://semiengineering.com/people/mike-rieger/)
## [Mike Bartley](https://semiengineering.com/people/mike-bartley/)
## [Mike Borza](https://semiengineering.com/people/mike-borza/)
## [Mike Chandler](https://semiengineering.com/people/mike-chandler/)
## [Mike Dini](https://semiengineering.com/people/mike-dini/)
## [Mike Farmwald](https://semiengineering.com/people/mike-farmwald/)
## [Mike Kliment](https://semiengineering.com/people/mike-kliment/)
## [Mike Lee](https://semiengineering.com/people/mike-lee/)
## [Mike Meredith](https://semiengineering.com/people/mike-meredith/)
## [Mike Scase](https://semiengineering.com/people/mike-scase/)
## [Mike Yungho Tsai](https://semiengineering.com/people/mike-yungho-tsai/)
## [Mikko Varpiola](https://semiengineering.com/people/mikko-varpiola/)
## [Milton R. Smith](https://semiengineering.com/people/milton-r-smith/)
## [Misha Burich](https://semiengineering.com/people/misha-burich/)
## [Mohamed Kassem](https://semiengineering.com/people/mohamed-kassem/)
## [Mohan R](https://semiengineering.com/people/mohan-r/)
## [Mojy Chian](https://semiengineering.com/people/mojy-chian/)
## [Morris Chang](https://semiengineering.com/people/morris-chang/)
## [Murat Alaybeyi](https://semiengineering.com/people/murat-alaybeyi/)
## [Mustafa Celik](https://semiengineering.com/people/mustafa-celik/)
## [Naeem Zafar](https://semiengineering.com/people/naeem-zafar/)
## [Nagesh Gupta](https://semiengineering.com/people/nagesh-gupta/)
## [Naveed Sherwani](https://semiengineering.com/people/naveed-sherwani/)
## [Naveen Chava](https://semiengineering.com/people/naveen-chava/)
## [Neil Johnson](https://semiengineering.com/people/neil-johnson/)
## [Neil Roberts](https://semiengineering.com/people/neil-roberts/)
## [Nick Cobb](https://semiengineering.com/people/nick-cobb/)
## [Nick Martin](https://semiengineering.com/people/nick-martin/)
## [Nick Martin](https://semiengineering.com/people/nick-martin-2/)
## [Nicky Lu](https://semiengineering.com/people/nicky-lu/)
## [Nicolas Delorme](https://semiengineering.com/people/nicolas-delorme/)
## [Ning Nan](https://semiengineering.com/people/ning-nan/)
## [Noah Sturcken](https://semiengineering.com/people/noah-sturcken/)
## [Norman Chang](https://semiengineering.com/people/norman-chang/)
## [Ole Christian Andersen](https://semiengineering.com/people/ole-christian-andersen/)
## [Olivier Lepape](https://semiengineering.com/people/olivier-lepape/)
## [Ori Braun](https://semiengineering.com/people/ori-braun/)
## [Oscar Buset](https://semiengineering.com/people/oscar-buset/)
## [P.T. Patel](https://semiengineering.com/people/p-t-patel/)
## [Pascal Peru](https://semiengineering.com/people/pascal-peru/)
## [Patrick J. Ready](https://semiengineering.com/people/patrick-j-ready/)
## [Paul Cunningham](https://semiengineering.com/people/paul-cunningham/)
## [Paul (Yen-Son) Huang](https://semiengineering.com/people/paul-yen-son-huang/)
## [Paul de Dood](https://semiengineering.com/people/paul-de-dood/)
## [Paul Harvell](https://semiengineering.com/people/paul-harvell/)
## [Paul Johnson](https://semiengineering.com/people/paul-johnson/)
## [Paul Levine](https://semiengineering.com/people/paul-levine/)
## [Paul Lindermann](https://semiengineering.com/people/paul-lindermann/)
## [Paul M. Hubbard](https://semiengineering.com/people/paul-m-hubbard/)
## [Paul Newhagen](https://semiengineering.com/people/paul-newhagen/)
## [Paul Nguon](https://semiengineering.com/people/paul-nguon/)
## [Paul Rodman](https://semiengineering.com/people/paul-rodman/)
## [Paul van Besouw](https://semiengineering.com/people/paul-van-besouw/)
## [Paul Wells](https://semiengineering.com/people/paul-wells/)
## [Peer Schmitt](https://semiengineering.com/people/peer-schmitt/)
## [Pengwei Qian](https://semiengineering.com/people/pengwei-qian/)
## [Pete Popov](https://semiengineering.com/people/pete-popov/)
## [Peter Eichenberger](https://semiengineering.com/people/peter-eichenberger/)
## [Peter Denyer](https://semiengineering.com/people/peter-denyer/)
## [Peter Flake](https://semiengineering.com/people/peter-flake/)
## [Peter Ivey](https://semiengineering.com/people/peter-ivey/)
## [Peter Meuris](https://semiengineering.com/people/peter-meuris/)
## [Peter Odryna](https://semiengineering.com/people/peter-odryna/)
## [Peter Petrov](https://semiengineering.com/people/peter-petrov/)
## [Peter Rip](https://semiengineering.com/people/peter-rip/)
## [Petro Estakhri](https://semiengineering.com/people/petro-estakhri/)
## [Phil Moorby](https://semiengineering.com/people/phil-moorby/)
## [Phil Tharp](https://semiengineering.com/people/phil-tharp/)
## [Philippe Boucard](https://semiengineering.com/people/philippe-boucard/)
## [Philippe Diehl](https://semiengineering.com/people/philippe-diehl/)
## [Philippe Duchene](https://semiengineering.com/people/philippe-duchene/)
## [Pierre Marty](https://semiengineering.com/people/pierre-marty/)
## [Prab Varma](https://semiengineering.com/people/prab-varma/)
## [Prabhat Aggarwal](https://semiengineering.com/people/prabhat-aggarwal/)
## [Prabhu Goel](https://semiengineering.com/people/prabhu-goel/)
## [Pradeep Fernandes](https://semiengineering.com/people/pradeep-fernandes/)
## [Pradeep Vajram](https://semiengineering.com/people/pradeep-vajram/)
## [Prakash Narain](https://semiengineering.com/people/prakash-narain/)
## [Pravin Madhani](https://semiengineering.com/people/pravin-madhani/)
## [R. Dean Adams](https://semiengineering.com/people/r-dean-adams/)
## [R. Mark Gogolewski](https://semiengineering.com/people/r-mark-gogolewski/)
## [R.K. Patil](https://semiengineering.com/people/r-k-patil/)
## [Raghavendra Mohan V](https://semiengineering.com/people/raghavendra-mohan-v/)
## [Raik Brinkmann](https://semiengineering.com/people/raik-brinkmann/)
## [Raj Raghavan](https://semiengineering.com/people/raj-raghavan/)
## [Rajeev Madhavan](https://semiengineering.com/people/rajeev-madhavan/)
## [Rajendran (Raj) Nair](https://semiengineering.com/people/rajendran-raj-nair/)
## [Rajit Manohar](https://semiengineering.com/people/rajit-manohar/)
## [Rajit Chandra](https://semiengineering.com/people/rajit-chandra/)
## [Rajiv Kumar](https://semiengineering.com/people/rajiv-kumar/)
## [Ralf Huuck](https://semiengineering.com/people/ralf-huuck/)
## [Ram S. Ramanujam](https://semiengineering.com/people/ram-s-ramanujam/)
## [Ramin Hojati](https://semiengineering.com/people/ramin-hojati/)
## [Ramy Iskander](https://semiengineering.com/people/ramy-iskander/)
## [Randy Eager](https://semiengineering.com/people/randy-eager/)
## [Randy Allen](https://semiengineering.com/people/randy-allen/)
## [Randy Caplan](https://semiengineering.com/people/randy-caplan/)
## [Randy Deffert](https://semiengineering.com/people/randy-deffert/)
## [Randy Rhea](https://semiengineering.com/people/randy-rhea/)
## [Raul Camposano](https://semiengineering.com/people/raul-camposano/)
## [Rauli Kaksonen](https://semiengineering.com/people/rauli-kaksonen/)
## [Ravender Goyal](https://semiengineering.com/people/ravender-goyal/)
## [Ravi Mehta](https://semiengineering.com/people/ravi-mehta/)
## [Ravi Shankar Rao](https://semiengineering.com/people/ravi-shankar-rao/)
## [Ravi Thummarukudy](https://semiengineering.com/people/ravi-thummarukudy/)
## [Ray Bulgar](https://semiengineering.com/people/ray-bulgar/)
## [Raymond Turin](https://semiengineering.com/people/raymond-turin/)
## [Reinhard Keil](https://semiengineering.com/people/reinhard-keil/)
## [RĂŠmi Butaud](https://semiengineering.com/people/rami-butaud/)
## [Rhonda Dirvin](https://semiengineering.com/people/rhonda-dirvin/)
## [Rich Witek](https://semiengineering.com/people/rich-witek/)
## [Richard C. (Dick) Foss](https://semiengineering.com/people/richard-c-dick-foss/)
## [Richard Chang](https://semiengineering.com/people/richard-chang/)
## [Richard Doherty](https://semiengineering.com/people/richard-doherty/)
## [Richard Meacham](https://semiengineering.com/people/richard-meacham/)
## [Richard Rudell](https://semiengineering.com/people/richard-rudell/)
## [Richard Taylor](https://semiengineering.com/people/richard-taylor/)
## [Richard Weber](https://semiengineering.com/people/richard-weber/)
## [Rick Carlson](https://semiengineering.com/people/rick-carlson/)
## [Rick Lazansky](https://semiengineering.com/people/rick-lazansky/)
## [Rob A. Rutenbar](https://semiengineering.com/people/rob-a-rutenbar/)
## [Rob Dekker](https://semiengineering.com/people/rob-dekker/)
## [Rob Gowin](https://semiengineering.com/people/rob-gowin/)
## [Robert Harland](https://semiengineering.com/people/robert-harland/)
## [Robert Kurshan](https://semiengineering.com/people/robert-kurshan/)
## [Robert Blackburn](https://semiengineering.com/people/robert-blackburn/)
## [Robert H. Dennard](https://semiengineering.com/people/robert-h-dennard/)
## [Robert Hartmann](https://semiengineering.com/people/robert-hartmann/)
## [Robert Noyce](https://semiengineering.com/people/robert-noyce/)
## [Robert Smith](https://semiengineering.com/people/robert-smith/)
## [Robi Dutta](https://semiengineering.com/people/robi-dutta/)
## [Roger Sturgeon](https://semiengineering.com/people/roger-sturgeon/)
## [Roger Gook](https://semiengineering.com/people/roger-gook/)
## [Ron Maxwell](https://semiengineering.com/people/ron-maxwell/)
## [Ronald A. Rohrer](https://semiengineering.com/people/ronald-a-rohrer/)
## [Ross Feeman](https://semiengineering.com/people/ross-feeman/)
## [Roy Prasad](https://semiengineering.com/people/roy-prasad/)
## [Sagar Reddy](https://semiengineering.com/people/sagar-reddy/)
## [Sailesh Kumar](https://semiengineering.com/people/sailesh-kumar/)
## [Sally Shlaer](https://semiengineering.com/people/sally-shlaer/)
## [Salvatore Carcia](https://semiengineering.com/people/salvatore-carcia/)
## [Sam Appleton](https://semiengineering.com/people/sam-appleton/)
## [Sam Kim](https://semiengineering.com/people/sam-kim/)
## [Samir Shroff](https://semiengineering.com/people/samir-shroff/)
## [Sandeep Srinivasan](https://semiengineering.com/people/sandeep-srinivasan/)
## [Sandipan Bhanot](https://semiengineering.com/people/sandipan-bhanot/)
## [Sang S. Wang](https://semiengineering.com/people/sang-s-wang/)
## [Sanjay Mittal](https://semiengineering.com/people/sanjay-mittal/)
## [Sanjay K Srivastava](https://semiengineering.com/people/sanjay-k-srivastava/)
## [Sarang Padalkar](https://semiengineering.com/people/sarang-padalkar/)
## [Satish Bagalkotkar](https://semiengineering.com/people/satish-bagalkotkar/)
## [Satish Padmanabhan](https://semiengineering.com/people/satish-padmanabhan/)
## [Satya Gupta](https://semiengineering.com/people/satya-gupta/)
## [Scott R. Powell](https://semiengineering.com/people/scott-r-powell/)
## [Scott T. Becker](https://semiengineering.com/people/scott-t-becker/)
## [Scott W. Houghton](https://semiengineering.com/people/scott-w-houghton/)
## [Sean Safarpour](https://semiengineering.com/people/sean-safarpour/)
## [Serge Maginot](https://semiengineering.com/people/serge-maginot/)
## [Seth Hallem](https://semiengineering.com/people/seth-hallem/)
## [Shahram Besharati](https://semiengineering.com/people/shahram-besharati/)
## [Shail Aditya](https://semiengineering.com/people/shail-aditya/)
## [Shajid Thiruvathodi](https://semiengineering.com/people/shajid-thiruvathodi/)
## [Shane Flint](https://semiengineering.com/people/shane-flint/)
## [Sharad Kapur](https://semiengineering.com/people/sharad-kapur/)
## [Shay Ben-Chorin](https://semiengineering.com/people/shay-ben-chorin/)
## [Shay Mizrachi](https://semiengineering.com/people/shay-mizrachi/)
## [Shen Lin](https://semiengineering.com/people/shen-lin/)
## [Sherif Eid](https://semiengineering.com/people/sherif-eid/)
## [Shiv Sikand](https://semiengineering.com/people/shiv-sikand/)
## [Shiv Tasker](https://semiengineering.com/people/shiv-tasker/)
## [Shubhodeep Roy Choudhury](https://semiengineering.com/people/shubhodeep-roy-choudhury/)
## [Simon Butler](https://semiengineering.com/people/simon-butler/)
## [Simon Davidmann](https://semiengineering.com/people/simon-davidmann/)
## [Simon Garrison](https://semiengineering.com/people/simon-garrison/)
## [Simon N. Springall](https://semiengineering.com/people/simon-n-springall/)
## [Snehanshu Shah](https://semiengineering.com/people/snehanshu-shah/)
## [Soo-Young Oh](https://semiengineering.com/people/soo-young-oh/)
## [Sotiris Bantast](https://semiengineering.com/people/sotiris-bantast/)
## [Srikanth Jadcherla](https://semiengineering.com/people/srikanth-jadcherla/)
## [Srinath Anantharaman](https://semiengineering.com/people/srinath-anantharaman/)
## [Srinivasan Durai](https://semiengineering.com/people/srinivasan-durai/)
## [Stanislav Ruev](https://semiengineering.com/people/stanislav-ruev/)
## [Stanley M. Hyduke](https://semiengineering.com/people/stanley-m-hyduke/)
## [Stanley Osher](https://semiengineering.com/people/stanley-osher/)
## [Stanley Yang](https://semiengineering.com/people/stanley-yang/)
## [Stefan Birman](https://semiengineering.com/people/stefan-birman/)
## [Stephane Hauradou](https://semiengineering.com/people/stephane-hauradou/)
## [StĂŠphane Leclercq](https://semiengineering.com/people/staphane-leclercq/)
## [Stephen Crosher](https://semiengineering.com/people/stephen-crosher/)
## [Stephen Fairbanks](https://semiengineering.com/people/stephen-fairbanks/)
## [Stephen J. Mellor](https://semiengineering.com/people/stephen-j-mellor/)
## [Steve Teig](https://semiengineering.com/people/steve-teig/)
## [Steve Bangert](https://semiengineering.com/people/steve-bangert/)
## [Steve Barlow](https://semiengineering.com/people/steve-barlow/)
## [Steve Carlson](https://semiengineering.com/people/steve-carlson/)
## [Steve Sapiro](https://semiengineering.com/people/steve-sapiro/)
## [Steve Walsh](https://semiengineering.com/people/steve-walsh/)
## [Steve White](https://semiengineering.com/people/steve-white/)
## [Steve Wilcox](https://semiengineering.com/people/steve-wilcox/)
## [Steve Yang](https://semiengineering.com/people/steve-yang/)
## [Steven Heinz](https://semiengineering.com/people/steven-heinz/)
## [Steven LâHer](https://semiengineering.com/people/steven-laeher/)
## [Steven Wang](https://semiengineering.com/people/steven-wang/)
## [Sudhir Kadkade](https://semiengineering.com/people/sudhir-kadkade/)
## [Sue Kunz](https://semiengineering.com/people/sue-kunz/)
## [Sujoy Chakravarty](https://semiengineering.com/people/sujoy-chakravarty/)
## [Sundar Iyer](https://semiengineering.com/people/sundar-iyer/)
## [Sundari Mitra](https://semiengineering.com/people/sundari-mitra/)
## [Sunil Jain](https://semiengineering.com/people/sunil-jain/)
## [Sunil Samel](https://semiengineering.com/people/sunil-samel/)
## [Sunil Talwar](https://semiengineering.com/people/sunil-talwar/)
## [Sycon Zohar](https://semiengineering.com/people/sycon-zohar/)
## [Sydney Lovely](https://semiengineering.com/people/sydney-lovely/)
## [Sylvian Kaiser](https://semiengineering.com/people/sylvian-kaiser/)
## [Tabor Smith](https://semiengineering.com/people/tabor-smith/)
## [Tae Hoon Song](https://semiengineering.com/people/tae-hoon-song/)
## [Tak Shigihara](https://semiengineering.com/people/tak-shigihara/)
## [Takis Breyiannis](https://semiengineering.com/people/takis-breyiannis/)
## [Tallis Blalack](https://semiengineering.com/people/tallis-blalack/)
## [Tapan Joshi](https://semiengineering.com/people/tapan-joshi/)
## [Tarak Parikh](https://semiengineering.com/people/tarak-parikh/)
## [Taylor Scanlon](https://semiengineering.com/people/taylor-scanlon/)
## [Terry Brewer](https://semiengineering.com/people/terry-brewer/)
## [Thomas Kailath](https://semiengineering.com/people/thomas-kailath/)
## [Thomas Niermann](https://semiengineering.com/people/thomas-niermann/)
## [Thomas Schultz](https://semiengineering.com/people/thomas-schultz/)
## [Tim Haynes](https://semiengineering.com/people/tim-haynes/)
## [Tobias Bjerregaard](https://semiengineering.com/people/tobias-bjerregaard/)
## [Todd Masey](https://semiengineering.com/people/todd-masey/)
## [Tom Paddock](https://semiengineering.com/people/tom-paddock/)
## [Tom Bruggere](https://semiengineering.com/people/tom-bruggere/)
## [Tom Cesear](https://semiengineering.com/people/tom-cesear/)
## [Tom Harris](https://semiengineering.com/people/tom-harris/)
## [Tom McWilliams](https://semiengineering.com/people/tom-mcwilliams/)
## [Tom Quarles](https://semiengineering.com/people/tom-quarles/)
## [Tony Curzon-Price](https://semiengineering.com/people/tony-curzon-price/)
## [Toshio Nakama](https://semiengineering.com/people/toshio-nakama/)
## [Trent McClements](https://semiengineering.com/people/trent-mcclements/)
## [Trent McConaghy](https://semiengineering.com/people/trent-mcconaghy/)
## [Uma Bondada](https://semiengineering.com/people/uma-bondada/)
## [Uri Tal](https://semiengineering.com/people/uri-tal/)
## [Vahagn Poghosyan](https://semiengineering.com/people/vahagn-poghosyan/)
## [Vaughn Betz](https://semiengineering.com/people/vaughn-betz/)
## [Venkat Iyer](https://semiengineering.com/people/venkat-iyer/)
## [Venugopal Kolathur](https://semiengineering.com/people/venugopal-kolathur/)
## [Victor Savenko](https://semiengineering.com/people/victor-savenko/)
## [Vigyan Singhal](https://semiengineering.com/people/vigyan-singhal/)
## [Vikram Jandhyala](https://semiengineering.com/people/vikram-jandhyala/)
## [Vincent Perrier](https://semiengineering.com/people/vincent-perrier/)
## [Vincent Thibaut](https://semiengineering.com/people/vincent-thibaut/)
## [Vinod K. Agarwal](https://semiengineering.com/people/vinod-k-agarwal/)
## [Vinod Kathail](https://semiengineering.com/people/vinod-kathail/)
## [Vinod Narayanan](https://semiengineering.com/people/vinod-narayanan/)
## [Virantha N. Ekanayake](https://semiengineering.com/people/virantha-n-ekanayake/)
## [Vishal Moondhra](https://semiengineering.com/people/vishal-moondhra/)
## [Vivek Raghavan](https://semiengineering.com/people/vivek-raghavan/)
## [Vivek Bhat](https://semiengineering.com/people/vivek-bhat/)
## [Vivek Pawar](https://semiengineering.com/people/vivek-pawar/)
## [Vlad Potanin](https://semiengineering.com/people/vlad-potanin/)
## [Vladimir Schellbach](https://semiengineering.com/people/vladimir-schellbach/)
## [Vojin Zivojnovic](https://semiengineering.com/people/vojin-zivojnovic/)
## [Wai Yan (William) Ho](https://semiengineering.com/people/wai-yan-william-ho/)
## [Walden (Wally) Rhines](https://semiengineering.com/people/walden-rhines/)
## [Wally Haas](https://semiengineering.com/people/wally-haas/)
## [Walter Chan](https://semiengineering.com/people/walter-chan/)
## [Walter Daems](https://semiengineering.com/people/walter-daems/)
## [Warren Savage](https://semiengineering.com/people/warren-savage/)
## [Wayne Dai](https://semiengineering.com/people/wayne-dai/)
## [Wayne Marking](https://semiengineering.com/people/wayne-marking/)
## [Weihua Sheng](https://semiengineering.com/people/weihua-sheng/)
## [Weiping (Peter) Shi](https://semiengineering.com/people/weiping-peter-shi/)
## [Weize Xie](https://semiengineering.com/people/weize-xie/)
## [Werner Geurts](https://semiengineering.com/people/werner-geurts/)
## [Will Herman](https://semiengineering.com/people/will-herman/)
## [Willem vanCleemput](https://semiengineering.com/people/willem-vancleemput/)
## [Willi Brandenburg](https://semiengineering.com/people/willi-brandenburg/)
## [William âBillâ Billowitch](https://semiengineering.com/people/william-aeoebillae%C2%9D-billowitch/)
## [Wim Schoenmaker](https://semiengineering.com/people/wim-schoenmaker/)
## [Wim Verhaegen](https://semiengineering.com/people/wim-verhaegen/)
## [Wlodek Kurjanowicz](https://semiengineering.com/people/wlodek-kurjanowicz/)
## [Wojciech Sakowski](https://semiengineering.com/people/wojciech-sakowski/)
## [Wolfram BĂźttner](https://semiengineering.com/people/wolfram-ba%C2%BCttner/)
## [Wu-Tung Cheng](https://semiengineering.com/people/wu-tung-cheng/)
## [WĹodzimierz Wrona](https://semiengineering.com/people/waodzimierz-wrona/)
## [Xerxes Wania](https://semiengineering.com/people/xerxes-wania/)
## [Xisheng Zhang](https://semiengineering.com/people/xisheng-zhang/)
## [Xuequn (Kevin) Xiang](https://semiengineering.com/people/xuequn-kevin-xiang/)
## [Yao-Ting Wang](https://semiengineering.com/people/yao-ting-wang/)
## [Yi (Bob) Xu](https://semiengineering.com/people/yi-bob-xu/)
## [Yoav Hollander](https://semiengineering.com/people/yoav-hollander/)
## [Yorgos Koutsoyannopoulost](https://semiengineering.com/people/yorgos-koutsoyannopoulost/)
## [Youn-Long (Steve) Lin](https://semiengineering.com/people/youn-long-steve-lin/)
## [Yuan Lu](https://semiengineering.com/people/yuan-lu/)
## [Yunshan Zhu](https://semiengineering.com/people/yunshan-zhu/)
## [Yuri Feinberg](https://semiengineering.com/people/yuri-feinberg/)
## [Z.M Simon Li](https://semiengineering.com/people/z-m-simon-li/)
## [Zhihong Liu](https://semiengineering.com/people/zhihong-liu/)
## [Zhonghai Lu](https://semiengineering.com/people/zhonghai-lu/)
## [Zied Marrakchi](https://semiengineering.com/people/zied-marrakchi/)
## [Zvi Or-Bach](https://semiengineering.com/people/zvi-or-bach/)
## [0-In Design Automation Inc.](https://semiengineering.com/entities/0-in-design-automation-inc/)
## [3Soft Corporation](https://semiengineering.com/entities/3soft-corporation/)
## [@HDL](https://semiengineering.com/entities/hdl/)
## [Aachen University of Technology](https://semiengineering.com/entities/aachen-university-of-technology/)
## [ACAD Corp](https://semiengineering.com/entities/acad-corp/)
## [Accel Technologies Inc.](https://semiengineering.com/entities/accel-technologies-inc/)
## [Accelerant Networks, Inc.](https://semiengineering.com/entities/accelerant-networks-inc/)
## [Accelerated Technology (UK) Ltd.](https://semiengineering.com/entities/accelerated-technology-uk-ltd/)
## [Accelerated Technology Inc.](https://semiengineering.com/entities/accelerated-technology-inc/)
## [Accelicon Technologies](https://semiengineering.com/entities/accelicon-technologies/)
## [Accellera](https://semiengineering.com/entities/accellera/)
## [Accellera Systems Initiative](https://semiengineering.com/entities/accellera-systems-initiative/)
## [Accellera UCIS WG](https://semiengineering.com/entities/accellera-ucis-wg/)
## [Accent S.R.L](https://semiengineering.com/entities/accent-s-r-l/)
## [Accolade Design Automation](https://semiengineering.com/entities/accolade-design-automation/)
## [ACEO Technology](https://semiengineering.com/entities/aceo-technology/)
## [Achronix Semiconductor Corporation](https://semiengineering.com/entities/achronix-semiconductor-corporation/)
## [Acorn Computer Group](https://semiengineering.com/entities/acorn-computer-group/)
## [Actel Corp.](https://semiengineering.com/entities/actel-corp/)
## [Adapt IP](https://semiengineering.com/entities/adapt-ip/)
## [ADAS Software](https://semiengineering.com/entities/adas-software/)
## [Adelante Technology](https://semiengineering.com/entities/adelante-technology/)
## [Adesto Technologies Corp.](https://semiengineering.com/entities/adesto-technologies-corp/)
## [Adicsys](https://semiengineering.com/entities/adicsys/)
## [Advanced CAM Technologies, Inc.](https://semiengineering.com/entities/advanced-cam-technologies-inc/)
## [Advanced Micro Devices (AMD)](https://semiengineering.com/entities/advanced-micro-devices-amd/)
## [Advanced Microelectronics](https://semiengineering.com/entities/advanced-microelectronics/)
## [Advanced RISC Machines Ltd.](https://semiengineering.com/entities/advanced-risc-machines-ltd/)
## [Advanced Technology Center](https://semiengineering.com/entities/advanced-technology-center/)
## [Advanced Test Technology, Inc.](https://semiengineering.com/entities/advanced-test-technology-inc/)
## [Advantest Corporation](https://semiengineering.com/entities/advantest-corporation/)
## [AGGIOS, Inc.](https://semiengineering.com/entities/aggios-inc/)
## [Agilent EEsof EDA](https://semiengineering.com/entities/agilent-eesof-eda/)
## [Agilent Technologies](https://semiengineering.com/entities/agilent-technologies/)
## [Agility Design Solutions](https://semiengineering.com/entities/agility-design-solutions/)
## [Agnisys, Inc.](https://semiengineering.com/entities/agnisys-inc/)
## [Alarity Corporation](https://semiengineering.com/entities/alarity-corporation/)
## [Alchemy Semiconductor](https://semiengineering.com/entities/alchemy-semiconductor/)
## [Aldec, Inc.](https://semiengineering.com/entities/aldec-inc/)
## [Algotochip Corporation](https://semiengineering.com/entities/algotochip-corporation/)
## [Allant Software](https://semiengineering.com/entities/allant-software/)
## [Allegro DVT](https://semiengineering.com/entities/allegro-dvt/)
## [Alphabit](https://semiengineering.com/entities/alphabit/)
## [Alphawave Semi](https://semiengineering.com/entities/alphawave-semi/)
## [Alta Group of Cadence](https://semiengineering.com/entities/alta-group-of-cadence/)
## [Altera Corporation](https://semiengineering.com/entities/altera-corporation/)
## [Altium, Inc.](https://semiengineering.com/entities/altium-inc/)
## [Altius Solutions Inc.](https://semiengineering.com/entities/altius-solutions-inc/)
## [Altos Design Automation, Inc.](https://semiengineering.com/entities/altos-design-automation-inc/)
## [Ambit Design Systems, Inc.](https://semiengineering.com/entities/ambit-design-systems-inc/)
## [AMIQ EDA](https://semiengineering.com/entities/amiq-eda/)
## [Amkor Technology](https://semiengineering.com/entities/amkor-technology/)
## [AMS AG](https://semiengineering.com/entities/ams-ag/)
## [Anacad Electrical Engineering Software GmbH](https://semiengineering.com/entities/anacad-electrical-engineering-software-gmbh/)
## [Anagram Inc.](https://semiengineering.com/entities/anagram-inc/)
## [Analog Bits Inc.](https://semiengineering.com/entities/analog-bits-inc/)
## [Analog Design Automation, Inc.](https://semiengineering.com/entities/analog-design-automation-inc/)
## [Analog Design Tools Inc.](https://semiengineering.com/entities/analog-design-tools-inc/)
## [Analogy Inc.](https://semiengineering.com/entities/analogy-inc/)
## [Anasim](https://semiengineering.com/entities/anasim/)
## [Andes Technology](https://semiengineering.com/entities/andes-technology/)
## [Andes Technology Corp.](https://semiengineering.com/entities/andes-technology-corp/)
## [Ansys](https://semiengineering.com/entities/ansys/)
## [Antares](https://semiengineering.com/entities/antares/)
## [Antrim Design Systems Inc.](https://semiengineering.com/entities/antrim-design-systems-inc/)
## [Apache Design Solutions, Inc.](https://semiengineering.com/entities/apache-design-solutions-inc/)
## [Apical Ltd.](https://semiengineering.com/entities/apical-ltd/)
## [APLAC Solutions Corp.](https://semiengineering.com/entities/aplac-solutions-corp/)
## [Aplus Design Technologies Inc.](https://semiengineering.com/entities/aplus-design-technologies-inc/)
## [Applied Materials, Inc.](https://semiengineering.com/entities/applied-materials-inc/)
## [Applied Simulation Technology](https://semiengineering.com/entities/applied-simulation-technology/)
## [Applied Wave Research, Inc.](https://semiengineering.com/entities/applied-wave-research-inc/)
## [Apres Technologies](https://semiengineering.com/entities/apres-technologies/)
## [Apteq Design Systems Inc.](https://semiengineering.com/entities/apteq-design-systems-inc/)
## [Aptix Corporation](https://semiengineering.com/entities/aptix-corporation/)
## [Arasan Chip Systems](https://semiengineering.com/entities/arasan-chip-systems/)
## [ARC International PLC](https://semiengineering.com/entities/arc-international-plc/)
## [Arcad SA](https://semiengineering.com/entities/arcad-sa/)
## [Arcadia Innovation, Inc.](https://semiengineering.com/entities/arcadia-innovation-inc/)
## [Archer Systems](https://semiengineering.com/entities/archer-systems/)
## [ArchPro Design Automation, Inc.](https://semiengineering.com/entities/archpro-design-automation-inc/)
## [ArcSys Inc.](https://semiengineering.com/entities/arcsys-inc/)
## [Arexsys S.A.](https://semiengineering.com/entities/arexsys-s-a/)
## [Argon Design Ltd.](https://semiengineering.com/entities/argon-design-ltd/)
## [Aristo Technology, Inc.](https://semiengineering.com/entities/aristo-technology-inc/)
## [Arithmatica](https://semiengineering.com/entities/arithmatica/)
## [Arium](https://semiengineering.com/entities/arium/)
## [Arkos Design Systems](https://semiengineering.com/entities/arkos-design-systems/)
## [Arkos Emulation Unit](https://semiengineering.com/entities/arkos-emulation-unit/)
## [Arm](https://semiengineering.com/entities/arm/)
## [Arrow Devices Pvt. Ltd.](https://semiengineering.com/entities/arrow-devices-pvt-ltd/)
## [ARS Microsystems Ltd.](https://semiengineering.com/entities/ars-microsystems-ltd/)
## [Arteris](https://semiengineering.com/entities/arterisip/)
## [Artisan Components, Inc.](https://semiengineering.com/entities/artisan-components-inc/)
## [ASE (Advanced Semiconductor Engineering)](https://semiengineering.com/entities/ase/)
## [ASML](https://semiengineering.com/entities/asml/)
## [Aspec Technology Inc](https://semiengineering.com/entities/aspec-technology-inc/)
## [ASSET InterTech](https://semiengineering.com/entities/asset-intertech/)
## [ASTC](https://semiengineering.com/entities/astc/)
## [Astronics Test Systems](https://semiengineering.com/entities/astronics-test-systems/)
## [Asygn](https://semiengineering.com/entities/asygn/)
## [Atair GmbH](https://semiengineering.com/entities/atair-gmbh/)
## [AtaiTec Corp.](https://semiengineering.com/entities/ataitec-corp/)
## [ATEEDA Ltd.](https://semiengineering.com/entities/ateeda-ltd/)
## [Atlantic Aerospace Electronics Corp.](https://semiengineering.com/entities/atlantic-aerospace-electronics-corp/)
## [ATopTech](https://semiengineering.com/entities/atoptech/)
## [Atrenta, Inc.](https://semiengineering.com/entities/atrenta-inc/)
## [Ausdia, Inc.](https://semiengineering.com/entities/ausdia-inc/)
## [AutoESL Design Technologies, Inc.](https://semiengineering.com/entities/autoesl-design-technologies-inc/)
## [Automated Integrated Design Systems](https://semiengineering.com/entities/automated-integrated-design-systems/)
## [Automated Systems, Inc.](https://semiengineering.com/entities/automated-systems-inc/)
## [Automatic Parallel Designs](https://semiengineering.com/entities/automatic-parallel-designs/)
## [Automotive Electronics Council (AEC)](https://semiengineering.com/entities/automotive-electronics-council-aec/)
## [Avalon Microelectronics Inc.](https://semiengineering.com/entities/avalon-microelectronics-inc/)
## [Avant! Corporation](https://semiengineering.com/entities/avant-corporation/)
## [Averant, Inc.](https://semiengineering.com/entities/averant-inc/)
## [AverStar](https://semiengineering.com/entities/averstar/)
## [Avery Design Systems](https://semiengineering.com/entities/avery-design-systems/)
## [Award Software](https://semiengineering.com/entities/award-software/)
## [Axiom Daterer Skandinavien AB](https://semiengineering.com/entities/axiom-daterer-skandinavien-ab/)
## [Axiom Design Automation](https://semiengineering.com/entities/axiom-design-automation/)
## [Axiomise](https://semiengineering.com/entities/axiomise/)
## [Axis Systems, Inc.](https://semiengineering.com/entities/axis-systems-inc/)
## [AXYS Design Automation, Inc.](https://semiengineering.com/entities/axys-design-automation-inc/)
## [Azuro, Inc.](https://semiengineering.com/entities/azuro-inc/)
## [A\|RT Technology of Adelante](https://semiengineering.com/entities/art-technology-of-adelante/)
## [Baya Systems](https://semiengineering.com/entities/baya-systems/)
## [BDTI](https://semiengineering.com/entities/bdti/)
## [Beach Solutions](https://semiengineering.com/entities/beach-solutions/)
## [Bell Labs DA group of Lucent](https://semiengineering.com/entities/bell-labs-da-group-of-lucent/)
## [Benelux B.V](https://semiengineering.com/entities/benelux-b-v/)
## [Berkeley Design Automation, Inc.](https://semiengineering.com/entities/berkeley-design-automation-inc/)
## [BlazeDFM](https://semiengineering.com/entities/blazedfm/)
## [Blue Cheetah](https://semiengineering.com/entities/blue-cheetah/)
## [Blue Pearl Software, Inc.](https://semiengineering.com/entities/blue-pearl-software-inc/)
## [Bluespec, Inc.](https://semiengineering.com/entities/bluespec-inc/)
## [BOPS, Inc.](https://semiengineering.com/entities/bops-inc/)
## [Boulder Creek Engineering](https://semiengineering.com/entities/boulder-creek-engineering/)
## [Brandenburg GmbH](https://semiengineering.com/entities/brandenburg-gmbh/)
## [Breker Verification Systems](https://semiengineering.com/entities/breker-verification-systems/)
## [Brewer Science](https://semiengineering.com/entities/brewer-science/)
## [Bridges2Silicon, Inc.](https://semiengineering.com/entities/bridges2silicon-inc/)
## [Brite Semiconductor](https://semiengineering.com/entities/brite-semiconductor/)
## [Broadcom](https://semiengineering.com/entities/broadcom/)
## [Bruker](https://semiengineering.com/entities/bruker/)
## [BTA Technology](https://semiengineering.com/entities/bta-technology/)
## [BTA Ultima Inc.](https://semiengineering.com/entities/bta-ultima-inc/)
## [C Level Design, Inc.](https://semiengineering.com/entities/c-level-design-inc/)
## [C2 Design Automation](https://semiengineering.com/entities/c2-design-automation/)
## [CAD Framework Initiative](https://semiengineering.com/entities/cad-framework-initiative/)
## [Cadabra Design Automation, Inc.](https://semiengineering.com/entities/cadabra-design-automation-inc/)
## [Cadence 802.11 wireless LAN IP](https://semiengineering.com/entities/cadence-802-11-wireless-lan-ip/)
## [Cadence Design Foundry](https://semiengineering.com/entities/cadence-design-foundry/)
## [Cadence Design Systems](https://semiengineering.com/entities/cadence-design-systems/)
## [Cadence PANTA IP cores](https://semiengineering.com/entities/cadence-panta-ip-cores/)
## [Cadis GmbH](https://semiengineering.com/entities/cadis-gmbh/)
## [CADIX Corporation](https://semiengineering.com/entities/cadix-corporation/)
## [CADIX ECAD division](https://semiengineering.com/entities/cadix-ecad-division/)
## [CadMOS Design Technology, Inc.](https://semiengineering.com/entities/cadmos-design-technology-inc/)
## [Cadnetix Corporation](https://semiengineering.com/entities/cadnetix-corporation/)
## [CAE systems](https://semiengineering.com/entities/cae-systems/)
## [CAE Technology Inc.](https://semiengineering.com/entities/cae-technology-inc/)
## [Caeco Inc.](https://semiengineering.com/entities/caeco-inc/)
## [Caedent Corporation](https://semiengineering.com/entities/caedent-corporation/)
## [Caetek Inc.](https://semiengineering.com/entities/caetek-inc/)
## [California Design Automation, Inc.](https://semiengineering.com/entities/california-design-automation-inc/)
## [Calma Company](https://semiengineering.com/entities/calma-company/)
## [Calypto Design Systems, Inc.](https://semiengineering.com/entities/calypto-design-systems-inc/)
## [Carbon Design Systems](https://semiengineering.com/entities/carbon-design-systems/)
## [CARDtools Systems](https://semiengineering.com/entities/cardtools-systems/)
## [Carnegie Mellon University](https://semiengineering.com/entities/carnegie-mellon-university/)
## [Cascade Semiconductor Solutions, Inc.](https://semiengineering.com/entities/cascade-semiconductor-solutions-inc/)
## [CAST, Inc.](https://semiengineering.com/entities/cast-inc/)
## [Catalytic Inc.](https://semiengineering.com/entities/catalytic-inc/)
## [Catapult C Product Division](https://semiengineering.com/entities/catapult-c-product-division/)
## [CEA](https://semiengineering.com/entities/cea/)
## [CEA-Leti](https://semiengineering.com/entities/cea-leti/)
## [Celestry Design Technologies Inc.](https://semiengineering.com/entities/celestry-design-technologies-inc/)
## [Celoxica Holding Plc.](https://semiengineering.com/entities/celoxica-holding-plc/)
## [Certess Inc.](https://semiengineering.com/entities/certess-inc/)
## [Certus Semiconductor](https://semiengineering.com/entities/certus-semiconductor/)
## [CEVA](https://semiengineering.com/entities/ceva/)
## [CheckLogic Systems inc.](https://semiengineering.com/entities/checklogic-systems-inc/)
## [Chip & Chip, Inc.](https://semiengineering.com/entities/chip-chip-inc/)
## [Chip Estimate Corp](https://semiengineering.com/entities/chip-estimate-corp/)
## [Chip Path Design Systems](https://semiengineering.com/entities/chip-path-design-systems/)
## [ChipAgents](https://semiengineering.com/entities/alpha-design-ai-chipagents/)
## [CHIPit business unit](https://semiengineering.com/entities/chipit-business-unit/)
## [ChipStart LLC](https://semiengineering.com/entities/chipstart-llc/)
## [Chronologic Simulation](https://semiengineering.com/entities/chronologic-simulation/)
## [Chronology Inc.](https://semiengineering.com/entities/chronology-inc/)
## [Chrysalis Symbolic Design, Inc.](https://semiengineering.com/entities/chrysalis-symbolic-design-inc/)
## [CIDA Technology, Inc.](https://semiengineering.com/entities/cida-technology-inc/)
## [CIM-Team GmbH](https://semiengineering.com/entities/cim-team-gmbh/)
## [CiraNova Inc.](https://semiengineering.com/entities/ciranova-inc/)
## [Clear Shape Technologies](https://semiengineering.com/entities/clear-shape-technologies/)
## [Cliosoft, Inc.](https://semiengineering.com/entities/cliosoft-inc/)
## [CLK Computer-Aided Design, Inc.](https://semiengineering.com/entities/clk-computer-aided-design-inc/)
## [CLK Design Automation, Inc.](https://semiengineering.com/entities/clk-design-automation-inc/)
## [Co-Design Automation, Inc.](https://semiengineering.com/entities/co-design-automation-inc/)
## [Codasip Ltd.](https://semiengineering.com/entities/codasip-ltd/)
## [Codefast, Inc](https://semiengineering.com/entities/codefast-inc/)
## [Codenomicon Oy](https://semiengineering.com/entities/codenomicon-oy/)
## [CodeSourcery Inc.](https://semiengineering.com/entities/codesourcery-inc/)
## [CoFluent Design](https://semiengineering.com/entities/cofluent-design/)
## [Cohu Inc.](https://semiengineering.com/entities/cohu/)
## [Comdisco Systems Inc.](https://semiengineering.com/entities/comdisco-systems-inc/)
## [ComLSI](https://semiengineering.com/entities/comlsi/)
## [Compact Model Coalition](https://semiengineering.com/entities/compact-model-council/)
## [Compass Design Automation](https://semiengineering.com/entities/compass-design-automation/)
## [Compiled Designs GmbH](https://semiengineering.com/entities/compiled-designs-gmbh/)
## [Computer Simulation Technology GmbH](https://semiengineering.com/entities/computer-simulation-technology-gmbh/)
## [Computervision, Inc.](https://semiengineering.com/entities/computervision-inc/)
## [Computing-Tabulating-Recording Company](https://semiengineering.com/entities/computing-tabulating-recording-company/)
## [Concept Engineering GmbH](https://semiengineering.com/entities/concept-engineering-gmbh/)
## [Context Corporation](https://semiengineering.com/entities/context-corporation/)
## [Contour Design Systems, Inc.](https://semiengineering.com/entities/contour-design-systems-inc/)
## [Conversant Intellectual Property Management](https://semiengineering.com/entities/conversant-intellectual-property-management/)
## [Cooper and Chyan Technology Inc.](https://semiengineering.com/entities/cooper-and-chyan-technology-inc/)
## [Cortus S.A.S.](https://semiengineering.com/entities/cortus-s-a-s/)
## [Cosmic Circuits](https://semiengineering.com/entities/cosmic-circuits/)
## [CoSoft Ltd.](https://semiengineering.com/entities/cosoft-ltd/)
## [Council of EDA Standards Committee](https://semiengineering.com/entities/council-of-eda-standards-committee/)
## [Coventor, a Lam Research Company](https://semiengineering.com/entities/coventor-inc/)
## [CoverMeter Tool](https://semiengineering.com/entities/covermeter-tool/)
## [CoWare LLC](https://semiengineering.com/entities/coware-llc/)
## [Coyote Systems](https://semiengineering.com/entities/coyote-systems/)
## [Cre8 Ventures](https://semiengineering.com/entities/cre8-ventures/)
## [Credence Systems Corporation](https://semiengineering.com/entities/credence-systems-corporation/)
## [Critical Blue](https://semiengineering.com/entities/critical-blue/)
## [Crosslight Software, Inc.](https://semiengineering.com/entities/crosslight-software-inc/)
## [CyberOptics, a Nordson Test & Inspection company](https://semiengineering.com/entities/cyberoptics/)
## [CycleC and other technology assets](https://semiengineering.com/entities/cyclec-and-other-technology-assets/)
## [Cycuity](https://semiengineering.com/entities/tortuga-logic/)
## [Cynapps](https://semiengineering.com/entities/cynapps/)
## [D2S](https://semiengineering.com/entities/d2s/)
## [Daisy Systems Corporation](https://semiengineering.com/entities/daisy-systems-corporation/)
## [Dassault Systèmes](https://semiengineering.com/entities/dassault-systa%C2%A8mes/)
## [Dasys](https://semiengineering.com/entities/dasys/)
## [Data I/O](https://semiengineering.com/entities/data-io/)
## [Datalink Far East, Ltd](https://semiengineering.com/entities/datalink-far-east-ltd/)
## [Dazix](https://semiengineering.com/entities/dazix/)
## [DDE-EDA A/S](https://semiengineering.com/entities/dde-eda-as/)
## [Deerbrook Systems Inc.](https://semiengineering.com/entities/deerbrook-systems-inc/)
## [Defacto Technologies](https://semiengineering.com/entities/defacto-technologies/)
## [Defense Advanced Research Agency (DARPA)](https://semiengineering.com/entities/defense-advanced-research-agency-darpa/)
## [DelSoft India Pvt. Ltd](https://semiengineering.com/entities/delsoft-india-pvt-ltd/)
## [DELTA Microelectronics](https://semiengineering.com/entities/delta-microelectronics/)
## [Denali Software, Inc.](https://semiengineering.com/entities/denali-software-inc/)
## [Desantage Corporation](https://semiengineering.com/entities/desantage-corporation/)
## [Descartes Automation Systems](https://semiengineering.com/entities/descartes-automation-systems/)
## [Descon InformationsSysteme GmbH](https://semiengineering.com/entities/descon-informationssysteme-gmbh/)
## [Design Acceleration Inc.](https://semiengineering.com/entities/design-acceleration-inc/)
## [DesignAdvance Systems Inc.](https://semiengineering.com/entities/designadvance-systems-inc/)
## [DesignPRO Inc.](https://semiengineering.com/entities/designpro-inc/)
## [DĂŠtente Technology, Inc.](https://semiengineering.com/entities/datente-technology-inc/)
## [Diablo Research Co. LLC](https://semiengineering.com/entities/diablo-research-co-llc/)
## [Digital Blocks](https://semiengineering.com/entities/digital-blocks/)
## [Dini Group](https://semiengineering.com/entities/dini-group/)
## [Docea Power](https://semiengineering.com/entities/docea-power/)
## [Dolphin Integration](https://semiengineering.com/entities/dolphin-integration/)
## [Dorado Design Automation, Inc.](https://semiengineering.com/entities/dorado-design-automation-inc/)
## [Doulos](https://semiengineering.com/entities/doulos/)
## [dQdt, Inc.](https://semiengineering.com/entities/dqdt-inc/)
## [DR YIELD](https://semiengineering.com/entities/dr-yield/)
## [DRC:DA](https://semiengineering.com/entities/drcda/)
## [DSM Technologies Inc.](https://semiengineering.com/entities/dsm-technologies-inc/)
## [DSP Division of Philips Semiconductor](https://semiengineering.com/entities/dsp-division-of-philips-semiconductor/)
## [Duolog Technologies Ltd.](https://semiengineering.com/entities/duolog-technologies-ltd/)
## [DXCorr Design, Inc.](https://semiengineering.com/entities/dxcorr-design-inc/)
## [Dynamic Soft analysis Inc.](https://semiengineering.com/entities/dynamic-soft-analysis-inc/)
## [E-Z-CAD, Inc.](https://semiengineering.com/entities/e-z-cad-inc/)
## [Eagle Design Automation](https://semiengineering.com/entities/eagle-design-automation/)
## [Eagleware, Inc.](https://semiengineering.com/entities/eagleware-inc/)
## [Eagleware-Elanix](https://semiengineering.com/entities/eagleware-elanix/)
## [eASIC Corporation](https://semiengineering.com/entities/easic-corporation/)
## [eBeam Initiative](https://semiengineering.com/entities/ebeam-initiative/)
## [eBizAutomation Inc.](https://semiengineering.com/entities/ebizautomation-inc/)
## [ECAD Inc.](https://semiengineering.com/entities/ecad-inc/)
## [Ăcole Polytechnique de MontrĂŠal](https://semiengineering.com/entities/a%E2%80%B0cole-polytechnique-de-montraal/)
## [ECSI](https://semiengineering.com/entities/ecsi/)
## [EDA Systems](https://semiengineering.com/entities/eda-systems/)
## [EDAC](https://semiengineering.com/entities/edac/)
## [EdXact SA](https://semiengineering.com/entities/edxact-sa/)
## [EEsof, Inc.](https://semiengineering.com/entities/eesof-inc/)
## [efabless.com](https://semiengineering.com/entities/efabless-com/)
## [Elanix, Inc.](https://semiengineering.com/entities/elanix-inc/)
## [Electronic System Design Alliance](https://semiengineering.com/entities/electronic-system-design-alliance/)
## [Eliyan](https://semiengineering.com/entities/eliyan/)
## [Elliptic Technologies](https://semiengineering.com/entities/elliptic-technologies/)
## [Elsip AB](https://semiengineering.com/entities/elsip-ab/)
## [EMA Design Automation](https://semiengineering.com/entities/ema-design-automation/)
## [Embedded Alley Solutions](https://semiengineering.com/entities/embedded-alley-solutions/)
## [Embedded Performance Inc.](https://semiengineering.com/entities/embedded-performance-inc/)
## [Embedded Solutions Limited](https://semiengineering.com/entities/embedded-solutions-limited/)
## [Embedded Vision Alliance](https://semiengineering.com/entities/embedded-vision-alliance/)
## [Emulation and Verification Engineering](https://semiengineering.com/entities/emulation-and-verification-engineering/)
## [Emulation division of Mitsui Bussan](https://semiengineering.com/entities/emulation-division-of-mitsui-bussan/)
## [EnSilica Ltd.](https://semiengineering.com/entities/ensilica-ltd/)
## [Entasys Design Inc.](https://semiengineering.com/entities/entasys-design-inc/)
## [EPIC Design Technology, Inc.](https://semiengineering.com/entities/epic-design-technology-inc/)
## [Escalade Corp.](https://semiengineering.com/entities/escalade-corp/)
## [eSilicon Corporation](https://semiengineering.com/entities/esilicon-corporation/)
## [ESL assets of Agility](https://semiengineering.com/entities/esl-assets-of-agility/)
## [ESL assets of Celoxica](https://semiengineering.com/entities/esl-assets-of-celoxica/)
## [Esperan Ltd.](https://semiengineering.com/entities/esperan-ltd/)
## [eTop Design Automation](https://semiengineering.com/entities/etop-design-automation/)
## [EuroMIPS Systems](https://semiengineering.com/entities/euromips-systems/)
## [European Design Center](https://semiengineering.com/entities/european-design-center/)
## [European Microelectronics Academy](https://semiengineering.com/entities/european-microelectronics-academy/)
## [EV Group](https://semiengineering.com/entities/ev-group/)
## [Evans Analytical Group](https://semiengineering.com/entities/evans-analytical-group/)
## [Evatronix IP Design Business](https://semiengineering.com/entities/evatronix-ip-design-business/)
## [Evatronix SA](https://semiengineering.com/entities/evatronix-sa/)
## [EverCAD Corporation](https://semiengineering.com/entities/evercad-corporation/)
## [Everest Design Automation, Inc.](https://semiengineering.com/entities/everest-design-automation-inc/)
## [Excellent Design Inc.](https://semiengineering.com/entities/excellent-design-inc/)
## [Excellicon Inc.](https://semiengineering.com/entities/excellicon-inc/)
## [Exemplar Logic, Inc.](https://semiengineering.com/entities/exemplar-logic-inc/)
## [Eximius Design](https://semiengineering.com/entities/eximius-design/)
## [Expedera](https://semiengineering.com/entities/expedera/)
## [ExperTest](https://semiengineering.com/entities/expertest/)
## [ExpertIO, Inc.](https://semiengineering.com/entities/expertio-inc/)
## [Expressive Systems](https://semiengineering.com/entities/expressive-systems/)
## [Extreme DA, Corp.](https://semiengineering.com/entities/extreme-da-corp/)
## [Fairchild Semiconductor](https://semiengineering.com/entities/fairchild-semiconductor/)
## [Falanx Microsystems AS](https://semiengineering.com/entities/falanx-microsystems-as/)
## [FEI â Knights Technology](https://semiengineering.com/entities/fei-knights-technology/)
## [FEI Company](https://semiengineering.com/entities/fei-company/)
## [Fenix Design Automation](https://semiengineering.com/entities/fenix-design-automation/)
## [Ferric Semiconductor Inc.](https://semiengineering.com/entities/ferric-semiconductor-inc/)
## [Fidus Systems Inc.](https://semiengineering.com/entities/fidus-systems-inc/)
## [First Earth Ltd.](https://semiengineering.com/entities/first-earth-ltd/)
## [FishTail Design Automation, Inc.](https://semiengineering.com/entities/fishtail-design-automation-inc/)
## [Flex Logix Technologies, Inc.](https://semiengineering.com/entities/flex-logix-technologies-inc/)
## [Flexras Technologies SAS](https://semiengineering.com/entities/flexras-technologies-sas/)
## [Flomerics EM software](https://semiengineering.com/entities/flomerics-em-software/)
## [Flomerics Group PLC](https://semiengineering.com/entities/flomerics-group-plc/)
## [Flometrics group Plc](https://semiengineering.com/entities/flometrics-group-plc/)
## [Flowmaster Ltd.](https://semiengineering.com/entities/flowmaster-ltd/)
## [FormFactor](https://semiengineering.com/entities/formfactor/)
## [Forte Design Systems](https://semiengineering.com/entities/forte-design-systems/)
## [FPGA technology of Kilopass](https://semiengineering.com/entities/fpga-technology-of-kilopass/)
## [Fractal Technologies](https://semiengineering.com/entities/fractal-technologies/)
## [Fraunhofer IIS EAS](https://semiengineering.com/entities/fraunhofer-iis-eas/)
## [Freescale â Virtual Garage](https://semiengineering.com/entities/freescale-virtual-garage/)
## [Freescale Semiconductor](https://semiengineering.com/entities/freescale-semiconductor/)
## [Frequency Technology](https://semiengineering.com/entities/frequency-technology/)
## [Frontier Design](https://semiengineering.com/entities/frontier-design/)
## [Frontline Design Automation, Inc.](https://semiengineering.com/entities/frontline-design-automation-inc/)
## [G-Analog Design Automation Ltd.](https://semiengineering.com/entities/g-analog-design-automation-ltd/)
## [Galaxy Semiconductor](https://semiengineering.com/entities/galaxy-semiconductor/)
## [Gambit Automated Design, Inc.](https://semiengineering.com/entities/gambit-automated-design-inc/)
## [Gatefield](https://semiengineering.com/entities/gatefield/)
## [GateRocket](https://semiengineering.com/entities/gaterocket/)
## [Gateway Design Automation](https://semiengineering.com/entities/gateway-design-automation/)
## [Gear Design Solutions, Inc.](https://semiengineering.com/entities/gear-design-solutions-inc/)
## [Gemini Design Technology Inc.](https://semiengineering.com/entities/gemini-design-technology-inc/)
## [Genedax](https://semiengineering.com/entities/genedax/)
## [Georgia Tech](https://semiengineering.com/entities/georgia-tech/)
## [Get2Chip Inc.](https://semiengineering.com/entities/get2chip-inc/)
## [Giga Scale Integration Corporation](https://semiengineering.com/entities/giga-scale-integration-corporation/)
## [Global Semiconductor Alliance](https://semiengineering.com/entities/global-semiconductor-alliance/)
## [Global Unichip Corp.](https://semiengineering.com/entities/global-unichip-corp/)
## [GlobalFoundries](https://semiengineering.com/entities/globalfoundries/)
## [Goanna Software Pty Ltd](https://semiengineering.com/entities/goanna-software-pty-ltd/)
## [Gold Standard Simulations Ltd.](https://semiengineering.com/entities/gold-standard-simulations-ltd/)
## [Gradient DAâs electrothermal analysis technology](https://semiengineering.com/entities/gradient-das-electrothermal-analysis-technology/)
## [Gradient Design Automation](https://semiengineering.com/entities/gradient-design-automation/)
## [Green Mountain Computing Systems](https://semiengineering.com/entities/green-mountain-computing-systems/)
## [Hammercores, Inc.](https://semiengineering.com/entities/hammercores-inc/)
## [HARDI Electronics AB](https://semiengineering.com/entities/hardi-electronics-ab/)
## [Harness Software Group](https://semiengineering.com/entities/harness-software-group/)
## [Hd Lab, K.K.](https://semiengineering.com/entities/hd-lab-k-k/)
## [HDAC Inc.](https://semiengineering.com/entities/hdac-inc/)
## [HDL Design House](https://semiengineering.com/entities/hdl-design-house/)
## [Helic, Inc.](https://semiengineering.com/entities/helic-inc/)
## [Helios Software Engineering Ltd.](https://semiengineering.com/entities/helios-software-engineering-ltd/)
## [Heterogeneous System Architecture (HSA) Foundation](https://semiengineering.com/entities/heterogeneous-system-architecture-hsa-foundation/)
## [Hewlett-Packard Company](https://semiengineering.com/entities/hewlett-packard-company/)
## [HHB assets](https://semiengineering.com/entities/hhb-assets/)
## [HHB Softron Inc.](https://semiengineering.com/entities/hhb-softron-inc/)
## [High Level Design Systems](https://semiengineering.com/entities/high-level-design-systems/)
## [HighIP Design Company](https://semiengineering.com/entities/highip-design-company/)
## [Hoschar AG](https://semiengineering.com/entities/hoschar-ag/)
## [HP Labs](https://semiengineering.com/entities/hp-labs/)
## [HPL Technologies, Inc.](https://semiengineering.com/entities/hpl-technologies-inc/)
## [Huins](https://semiengineering.com/entities/huins/)
## [Hunter and Ready](https://semiengineering.com/entities/hunter-and-ready/)
## [HyperLynx, Inc.](https://semiengineering.com/entities/hyperlynx-inc/)
## [IBM](https://semiengineering.com/entities/ibm/)
## [IBM â Altium group](https://semiengineering.com/entities/ibm-altium-group/)
## [IBM Foundry](https://semiengineering.com/entities/ibm-foundry/)
## [IC Manage](https://semiengineering.com/entities/ic-manage/)
## [ICScape, Inc.](https://semiengineering.com/entities/icscape-inc/)
## [ICUCOM Corporation](https://semiengineering.com/entities/icucom-corporation/)
## [IEC](https://semiengineering.com/entities/iec/)
## [IEEE](https://semiengineering.com/entities/ieee/)
## [IEEE 1800.2](https://semiengineering.com/entities/ieee-1800-2/)
## [IEEE DASC](https://semiengineering.com/entities/ieee-dasc/)
## [IEEE SA](https://semiengineering.com/entities/ieee-sa/)
## [IKOS Systems, Inc.](https://semiengineering.com/entities/ikos-systems-inc/)
## [Imagination Technologies](https://semiengineering.com/entities/imagination-technologies/)
## [Imec](https://semiengineering.com/entities/imec/)
## [iMODL](https://semiengineering.com/entities/imodl/)
## [Imperas Inc.](https://semiengineering.com/entities/imperas-inc/)
## [Impinj](https://semiengineering.com/entities/impinj/)
## [impinj NVM IP](https://semiengineering.com/entities/impinj-nvm-ip/)
## [IMS](https://semiengineering.com/entities/ims/)
## [In-Chip Systems](https://semiengineering.com/entities/in-chip-systems/)
## [INCASES Engineering GmbH](https://semiengineering.com/entities/incases-engineering-gmbh/)
## [Incentia Design Systems](https://semiengineering.com/entities/incentia-design-systems/)
## [Independent Design Automation Companies](https://semiengineering.com/entities/independent-design-automation-companies/)
## [Infineon Technologies](https://semiengineering.com/entities/infineon-technologies/)
## [Infiniscale](https://semiengineering.com/entities/infiniscale/)
## [Infinite Designs Ltd.](https://semiengineering.com/entities/infinite-designs-ltd/)
## [Ingenuus Corporation](https://semiengineering.com/entities/ingenuus-corporation/)
## [Ingot Systems](https://semiengineering.com/entities/ingot-systems/)
## [InnoLogic Systems, Inc.](https://semiengineering.com/entities/innologic-systems-inc/)
## [Innotech Corporation](https://semiengineering.com/entities/innotech-corporation/)
## [Innovative CAD Software, Inc.](https://semiengineering.com/entities/innovative-cad-software-inc/)
## [Innoveda, Inc.](https://semiengineering.com/entities/innoveda-inc/)
## [INRIA](https://semiengineering.com/entities/inria/)
## [inSilicon Corporation](https://semiengineering.com/entities/insilicon-corporation/)
## [InSpec Validation System](https://semiengineering.com/entities/inspec-validation-system/)
## [Instigate CJSC](https://semiengineering.com/entities/instigate-cjsc/)
## [Integrand Software](https://semiengineering.com/entities/integrand-software/)
## [Integrated Measurements Systems, Inc.](https://semiengineering.com/entities/integrated-measurements-systems-inc/)
## [Integrated Silicon Systems, Inc.](https://semiengineering.com/entities/integrated-silicon-systems-inc/)
## [Integrated Systems Engineering AG](https://semiengineering.com/entities/integrated-systems-engineering-ag/)
## [Integrity Engineering, Inc.](https://semiengineering.com/entities/integrity-engineering-inc/)
## [Intel Corp.](https://semiengineering.com/entities/intel-corp/)
## [Intel PLD business](https://semiengineering.com/entities/intel-pld-business/)
## [Intelligent Systems Japan, KK](https://semiengineering.com/entities/intelligent-systems-japan-kk/)
## [Intento Design](https://semiengineering.com/entities/intento-design/)
## [Interconnectix Inc.](https://semiengineering.com/entities/interconnectix-inc/)
## [Interfaces Technical Committee](https://semiengineering.com/entities/interfaces-technical-committee/)
## [Intergraph Electronics](https://semiengineering.com/entities/intergraph-electronics/)
## [Intergraph Inc.](https://semiengineering.com/entities/intergraph-inc/)
## [interHDL](https://semiengineering.com/entities/interhdl/)
## [Intermetrics](https://semiengineering.com/entities/intermetrics/)
## [Intermetrics VHDL simulator](https://semiengineering.com/entities/intermetrics-vhdl-simulator/)
## [International Organization of Standards](https://semiengineering.com/entities/international-organization-of-standards/)
## [Interra IT](https://semiengineering.com/entities/interra-it/)
## [InTime Software](https://semiengineering.com/entities/intime-software/)
## [Invarian, Inc.](https://semiengineering.com/entities/invarian-inc/)
## [Invarium, Inc.](https://semiengineering.com/entities/invarium-inc/)
## [Inventra](https://semiengineering.com/entities/inventra/)
## [Inventure Inc.](https://semiengineering.com/entities/inventure-inc/)
## [Invionics Inc.](https://semiengineering.com/entities/invionics-inc/)
## [IOTA Technology Inc.](https://semiengineering.com/entities/iota-technology-inc/)
## [IPextreme, Inc.](https://semiengineering.com/entities/ipextreme-inc/)
## [iRoC Technologies SA](https://semiengineering.com/entities/iroc-technologies-sa/)
## [ISSC Technology Corporation](https://semiengineering.com/entities/issc-technology-corporation/)
## [Japanese customers of Cadence software](https://semiengineering.com/entities/japanese-customers-of-cadence-software/)
## [Jasper Design Automation](https://semiengineering.com/entities/jasper-design-automation/)
## [Jazz Semiconductor, Inc.](https://semiengineering.com/entities/jazz-semiconductor-inc/)
## [JCET](https://semiengineering.com/entities/jcet/)
## [Jedat Inc.](https://semiengineering.com/entities/jedat-inc/)
## [JEDEC](https://semiengineering.com/entities/jedec/)
## [Juniper Networks, Inc.](https://semiengineering.com/entities/juniper-networks-inc/)
## [K2 Technologies, Inc.](https://semiengineering.com/entities/k2-technologies-inc/)
## [Kandou Bus](https://semiengineering.com/entities/kandou-bus/)
## [Keil](https://semiengineering.com/entities/keil/)
## [Keysight Technologies](https://semiengineering.com/entities/keysight-technologies/)
## [Kilopass Technology Inc.](https://semiengineering.com/entities/kilopass-technology-inc/)
## [Kimotion Technologies](https://semiengineering.com/entities/kimotion-technologies/)
## [KLA](https://semiengineering.com/entities/kla-tencor/)
## [KLA-Tencor](https://semiengineering.com/entities/kla-tencor-2/)
## [Knowlent Corporation](https://semiengineering.com/entities/knowlent-corporation/)
## [Kozio, Inc.](https://semiengineering.com/entities/kozio-inc/)
## [L-3 Communications](https://semiengineering.com/entities/l-3-communications/)
## [Lam Research](https://semiengineering.com/entities/lam-research/)
## [Lattice Semiconductor](https://semiengineering.com/entities/lattice-semiconductor/)
## [Leda Design, Inc.](https://semiengineering.com/entities/leda-design-inc/)
## [Leda SA](https://semiengineering.com/entities/leda-sa/)
## [Leuven Industrial Software Company](https://semiengineering.com/entities/leuven-industrial-software-company/)
## [Library Technologies, Inc.](https://semiengineering.com/entities/library-technologies-inc/)
## [Lighthouse Design Automation, Inc.](https://semiengineering.com/entities/lighthouse-design-automation-inc/)
## [Logic Automation, Inc.](https://semiengineering.com/entities/logic-automation-inc/)
## [Logic Modeling Corporation](https://semiengineering.com/entities/logic-modeling-corporation/)
## [Logic Modeling Systems Inc.](https://semiengineering.com/entities/logic-modeling-systems-inc/)
## [Logical Devices, Inc.](https://semiengineering.com/entities/logical-devices-inc/)
## [LogicVision, Inc.](https://semiengineering.com/entities/logicvision-inc/)
## [Logipard AB](https://semiengineering.com/entities/logipard-ab/)
## [Looking Glass Studios](https://semiengineering.com/entities/looking-glass-studios/)
## [Lorentz Solution, Inc.](https://semiengineering.com/entities/lorentz-solution-inc/)
## [LSI Logic](https://semiengineering.com/entities/lsi-logic/)
## [Luminescent Mask Synthesis technology](https://semiengineering.com/entities/luminescent-mask-synthesis-technology/)
## [Luminescent Technologies](https://semiengineering.com/entities/luminescent-technologies/)
## [Magillem](https://semiengineering.com/entities/magillem/)
## [Magma Design Automation Inc.](https://semiengineering.com/entities/magma-design-automation-inc/)
## [Magwel NV](https://semiengineering.com/entities/magwel-nv/)
## [Marple Technologies](https://semiengineering.com/entities/marple-technologies/)
## [Marvell Technology](https://semiengineering.com/entities/marvell-technology-group-ltd/)
## [Massachusetts Institute of Technology](https://semiengineering.com/entities/massachusetts-institute-of-technology/)
## [Massteck Ltd.](https://semiengineering.com/entities/massteck-ltd/)
## [Mathtools Ltd](https://semiengineering.com/entities/mathtools-ltd/)
## [Mathworks](https://semiengineering.com/entities/mathworks/)
## [Maxim Integrated Inc.](https://semiengineering.com/entities/maxim-integrated-inc/)
## [Memory BIST Division of iRoC](https://semiengineering.com/entities/memory-bist-division-of-iroc/)
## [Menta](https://semiengineering.com/entities/menta/)
## [Mentor Embedded Systems Division](https://semiengineering.com/entities/mentor-embedded-systems-division/)
## [Mentor Emulation Division](https://semiengineering.com/entities/mentor-emulation-division/)
## [Mentor Mechanical Analysis Division](https://semiengineering.com/entities/mentor-mechanical-analysis-division/)
## [Mentor physical libraries](https://semiengineering.com/entities/mentor-physical-libraries/)
## [Mercel AB](https://semiengineering.com/entities/mercel-ab/)
## [Mercel AUTOSAR assets](https://semiengineering.com/entities/mercel-autosar-assets/)
## [Meropa Inc.](https://semiengineering.com/entities/meropa-inc/)
## [Meta Systems SARL](https://semiengineering.com/entities/meta-systems-sarl/)
## [Meta-Software Inc.](https://semiengineering.com/entities/meta-software-inc/)
## [Metamor Inc.](https://semiengineering.com/entities/metamor-inc/)
## [MetaWare Inc.](https://semiengineering.com/entities/metaware-inc/)
## [Methodics, Inc.](https://semiengineering.com/entities/methodics-inc/)
## [Micro Magic EDA assets](https://semiengineering.com/entities/micro-magic-eda-assets/)
## [Micro Magic, Inc.](https://semiengineering.com/entities/micro-magic-inc/)
## [Microchip Technology, Inc.](https://semiengineering.com/entities/microchip-technology-inc/)
## [Microcode Engineering Inc.](https://semiengineering.com/entities/microcode-engineering-inc/)
## [Microcosm Technologies Inc.](https://semiengineering.com/entities/microcosm-technologies-inc/)
## [Microelectronics Research & Development Ltd.](https://semiengineering.com/entities/microelectronics-research-development-ltd/)
## [Micrologic Solutions Limited](https://semiengineering.com/entities/micrologic-solutions-limited/)
## [Microsemi Corporation](https://semiengineering.com/entities/microsemi-corporation/)
## [MicroSim Corp](https://semiengineering.com/entities/microsim-corp/)
## [Microtec Research, Inc.](https://semiengineering.com/entities/microtec-research-inc/)
## [Microtronic](https://semiengineering.com/entities/microtronic/)
## [Mint Technology](https://semiengineering.com/entities/mint-technology/)
## [MIPI Alliance](https://semiengineering.com/entities/mipi-alliance/)
## [MIPS Analog Business Group](https://semiengineering.com/entities/mips-analog-business-group/)
## [MIPS Technologies](https://semiengineering.com/entities/mips-technologies/)
## [Mirabilis Design](https://semiengineering.com/entities/mirabilis-design/)
## [Missing Link Tools](https://semiengineering.com/entities/missing-link-tools/)
## [MITRE Engenuity](https://semiengineering.com/entities/mitre-engenuity/)
## [Mitsui Bussan Digital Corp](https://semiengineering.com/entities/mitsui-bussan-digital-corp/)
## [Mixel, Inc.](https://semiengineering.com/entities/mixel-inc/)
## [Mobiveil, Inc.](https://semiengineering.com/entities/mobiveil-inc/)
## [Model Technology Inc.](https://semiengineering.com/entities/model-technology-inc/)
## [Modus Test](https://semiengineering.com/entities/modus-test/)
## [Mojave, Inc.](https://semiengineering.com/entities/mojave-inc/)
## [MonolithIC 3D Inc](https://semiengineering.com/entities/monolithic-3d-inc/)
## [Monterey Design Systems, Inc.](https://semiengineering.com/entities/monterey-design-systems-inc/)
## [Moortec Semiconductor Ltd.](https://semiengineering.com/entities/moortec-semiconductor-ltd/)
## [Morfik Technology Pty Ltd.](https://semiengineering.com/entities/morfik-technology-pty-ltd/)
## [MOSAID SIP assets](https://semiengineering.com/entities/mosaid-sip-assets/)
## [MOSAID Technologies Inc.](https://semiengineering.com/entities/mosaid-technologies-inc/)
## [Moscape, Inc](https://semiengineering.com/entities/moscape-inc/)
## [MOSIS](https://semiengineering.com/entities/mosis/)
## [Mosys SerDes IP](https://semiengineering.com/entities/mosys-serdes-ip/)
## [MoSys, Inc.](https://semiengineering.com/entities/mosys-inc/)
## [Movellus](https://semiengineering.com/entities/movellus/)
## [Multicore Association](https://semiengineering.com/entities/multicore-association/)
## [MunEDA GmbH](https://semiengineering.com/entities/muneda-gmbh/)
## [NanGate, Inc.](https://semiengineering.com/entities/nangate-inc/)
## [Nannor Technologies Inc.](https://semiengineering.com/entities/nannor-technologies-inc/)
## [Nascentric, Inc.](https://semiengineering.com/entities/nascentric-inc/)
## [Nassda Corporation](https://semiengineering.com/entities/nassda-corporation/)
## [National Research Council of Canada](https://semiengineering.com/entities/national-research-council-of-canada/)
## [National Semiconducor](https://semiengineering.com/entities/national-semiconducor/)
## [Neolinear, Inc.](https://semiengineering.com/entities/neolinear-inc/)
## [NetSpeed Systems](https://semiengineering.com/entities/netspeed-systems/)
## [Network Design Tools, Inc.](https://semiengineering.com/entities/network-design-tools-inc/)
## [NeuroCAD Inc.](https://semiengineering.com/entities/neurocad-inc/)
## [Nexsyn Design Technology Inc](https://semiengineering.com/entities/nexsyn-design-technology-inc/)
## [Next Device Limited](https://semiengineering.com/entities/next-device-limited/)
## [NextOp Software, Inc.](https://semiengineering.com/entities/nextop-software-inc/)
## [NI (formerly National Instruments)](https://semiengineering.com/entities/national-instruments/)
## [Nimbic, Inc.](https://semiengineering.com/entities/nimbic-inc/)
## [NM Electronics](https://semiengineering.com/entities/nm-electronics/)
## [Northwest Logic, Inc.](https://semiengineering.com/entities/northwest-logic-inc/)
## [Nova](https://semiengineering.com/entities/nova/)
## [Novarm Limited](https://semiengineering.com/entities/novarm-limited/)
## [Novas Software](https://semiengineering.com/entities/novas-software/)
## [Novelics](https://semiengineering.com/entities/novelics/)
## [Novo Systems Corp](https://semiengineering.com/entities/novo-systems-corp/)
## [Novocell Semiconductor, Inc.](https://semiengineering.com/entities/novocell-semiconductor-inc/)
## [NP Komplete Technologies BV](https://semiengineering.com/entities/np-komplete-technologies-bv/)
## [nSys Design Systems Private Limited](https://semiengineering.com/entities/nsys-design-systems-private-limited/)
## [Numerical Technologies, Inc.](https://semiengineering.com/entities/numerical-technologies-inc/)
## [NuPGA](https://semiengineering.com/entities/nupga/)
## [Nusym Technology, Inc.](https://semiengineering.com/entities/nusym-technology-inc/)
## [NXP CMOS IP](https://semiengineering.com/entities/nxp-cmos-ip/)
## [NXP Semiconductor](https://semiengineering.com/entities/nxp-semiconductor/)
## [Oasys Design Systems Inc.](https://semiengineering.com/entities/oasys-design-systems-inc/)
## [Obsidian Software](https://semiengineering.com/entities/obsidian-software/)
## [OCP-IP](https://semiengineering.com/entities/ocp-ip/)
## [Omnicad Corp.](https://semiengineering.com/entities/omnicad-corp/)
## [OneSpin Solutions GmbH](https://semiengineering.com/entities/onespin-solutions-gmbh/)
## [Onto Innovation](https://semiengineering.com/entities/onto-innovation/)
## [OPC Technology](https://semiengineering.com/entities/opc-technology/)
## [Open Networks Engineering](https://semiengineering.com/entities/open-networks-engineering/)
## [Open SystemC Initiative](https://semiengineering.com/entities/open-systemc-initiatve/)
## [Open Verilog International](https://semiengineering.com/entities/open-verilog-international/)
## [Open Virtual Platforms](https://semiengineering.com/entities/open-virtual-platforms/)
## [Open-Silicon, Inc.](https://semiengineering.com/entities/open-silicon-inc/)
## [OptEM Engineering Inc.](https://semiengineering.com/entities/optem-engineering-inc/)
## [Optic2Connect Pte Ltd](https://semiengineering.com/entities/optic2connect-pte-ltd/)
## [Optical Internetworking Forum (OIF)](https://semiengineering.com/entities/optical-internetworking-forum-oif/)
## [Optical Research Associates LLC](https://semiengineering.com/entities/optical-research-associates-llc/)
## [Optimal Corporation](https://semiengineering.com/entities/optimal-corporation/)
## [Optimal Solutions, Inc.](https://semiengineering.com/entities/optimal-solutions-inc/)
## [OptimalPlus](https://semiengineering.com/entities/optimal-plus/)
## [OrCAD](https://semiengineering.com/entities/orcad/)
## [Oski Technology](https://semiengineering.com/entities/oski-technology/)
## [Out of Business](https://semiengineering.com/entities/out-of-business/)
## [Pacer Infotec Inc.](https://semiengineering.com/entities/pacer-infotec-inc/)
## [PADS Software Inc.](https://semiengineering.com/entities/pads-software-inc/)
## [Palmchip Corporation](https://semiengineering.com/entities/palmchip-corporation/)
## [Palmchip interface IP](https://semiengineering.com/entities/palmchip-interface-ip/)
## [Panel Level Packaging Consortium (PLC)](https://semiengineering.com/entities/panel-level-packaging-consortium-plc/)
## [Paradigm Works](https://semiengineering.com/entities/paradigm-works/)
## [Parsec Software Inc.](https://semiengineering.com/entities/parsec-software-inc/)
## [PCB Libraries Inc.](https://semiengineering.com/entities/pcb-libraries-inc/)
## [PCB Matrix Corporation](https://semiengineering.com/entities/pcb-matrix-corporation/)
## [PDF Solutions](https://semiengineering.com/entities/pdf-solutions/)
## [Performance CAD](https://semiengineering.com/entities/performance-cad/)
## [Performance Signal Integrity, Inc.](https://semiengineering.com/entities/performance-signal-integrity-inc/)
## [Performance-IP, LLC.](https://semiengineering.com/entities/performance-ip-llc/)
## [Personal CAD Systems](https://semiengineering.com/entities/personal-cad-systems/)
## [Pextra Corporation](https://semiengineering.com/entities/pextra-corporation/)
## [Philips Semiconductor](https://semiengineering.com/entities/philips-semiconductor/)
## [Phoenix Technologies Ltd.](https://semiengineering.com/entities/phoenix-technologies-ltd/)
## [Physware, Inc.](https://semiengineering.com/entities/physware-inc/)
## [PiE Design Systems Inc.](https://semiengineering.com/entities/pie-design-systems-inc/)
## [Pinebush Technologies](https://semiengineering.com/entities/pinebush-technologies/)
## [Plato Design Systems](https://semiengineering.com/entities/plato-design-systems/)
## [PLDA](https://semiengineering.com/entities/plda/)
## [Pleiades Design and Test Technologies Inc.](https://semiengineering.com/entities/pleiades-design-and-test-technologies-inc/)
## [Plunify Pte Ltd](https://semiengineering.com/entities/plunify-pte-ltd/)
## [Pollen Technology](https://semiengineering.com/entities/pollen-technology/)
## [PolySpace Technologies](https://semiengineering.com/entities/polyspace-technologies/)
## [Ponte Solutions Inc.](https://semiengineering.com/entities/ponte-solutions-inc/)
## [Portable Stimulus Working Group (PSWG)](https://semiengineering.com/entities/portable-stimulus-working-group/)
## [PowerEscape, Inc.](https://semiengineering.com/entities/powerescape-inc/)
## [Praesagus, Inc.](https://semiengineering.com/entities/praesagus-inc/)
## [Precedence Inc.](https://semiengineering.com/entities/precedence-inc/)
## [Precim Corp](https://semiengineering.com/entities/precim-corp/)
## [Precise Software Technologies Inc](https://semiengineering.com/entities/precise-software-technologies-inc/)
## [ProDesign Electronic GmbH](https://semiengineering.com/entities/prodesign-electronic-gmbh/)
## [Progressant Technologies, Inc.](https://semiengineering.com/entities/progressant-technologies-inc/)
## [Project Technology Inc.](https://semiengineering.com/entities/project-technology-inc/)
## [Prolific, Inc.](https://semiengineering.com/entities/prolific-inc/)
## [Promex Industries](https://semiengineering.com/entities/promex-industries/)
## [ProPlus Design Solutions, Inc.](https://semiengineering.com/entities/proplus-design-solutions-inc/)
## [ProSoft Oy](https://semiengineering.com/entities/prosoft-oy/)
## [proteanTecs](https://semiengineering.com/entities/proteantecs/)
## [Protecode](https://semiengineering.com/entities/protecode/)
## [Protel International Pty, Ltd.](https://semiengineering.com/entities/protel-international-pty-ltd/)
## [Provis Corporation](https://semiengineering.com/entities/provis-corporation/)
## [prpl foundation](https://semiengineering.com/entities/prpl-foundation/)
## [Pulsic](https://semiengineering.com/entities/pulsic/)
## [Pyxis Technology](https://semiengineering.com/entities/pyxis-technology/)
## [Q Design Automation](https://semiengineering.com/entities/q-design-automation/)
## [Q Point Technology](https://semiengineering.com/entities/q-point-technology/)
## [QP Technologies](https://semiengineering.com/entities/quik-pak/)
## [QPX GmbH](https://semiengineering.com/entities/qpx-gmbh/)
## [Quad Design Technology, Inc.](https://semiengineering.com/entities/quad-design-technology-inc/)
## [Quadric](https://semiengineering.com/entities/quadric/)
## [Quadtree Software Corporation](https://semiengineering.com/entities/quadtree-software-corporation/)
## [Qualcomm Incorporated](https://semiengineering.com/entities/qualcomm-incorporated/)
## [Qualis, Inc.](https://semiengineering.com/entities/qualis-inc/)
## [Quickturn Design Systems, Inc.](https://semiengineering.com/entities/quickturn-design-systems-inc/)
## [R3Logic, Inc.](https://semiengineering.com/entities/r3logic-inc/)
## [Racal Redac](https://semiengineering.com/entities/racal-redac/)
## [Racal Redac â VHDL simulator](https://semiengineering.com/entities/racal-redac-vhdl-simulator/)
## [Racal Redac SilcSyn](https://semiengineering.com/entities/racal-redac-silcsyn/)
## [Radiant Design Tools, Inc.](https://semiengineering.com/entities/radiant-design-tools-inc/)
## [Rambus, Inc.](https://semiengineering.com/entities/rambus-inc/)
## [Random Logic Corporation](https://semiengineering.com/entities/random-logic-corporation/)
## [RAPID](https://semiengineering.com/entities/rapid/)
## [RaveSim, Inc.](https://semiengineering.com/entities/ravesim-inc/)
## [RAVIcad Inc.](https://semiengineering.com/entities/ravicad-inc/)
## [Ready Systems](https://semiengineering.com/entities/ready-systems/)
## [Real Intent, Inc.](https://semiengineering.com/entities/real-intent-inc/)
## [Redwood Design Automation](https://semiengineering.com/entities/redwood-design-automation/)
## [Renesas Electronics](https://semiengineering.com/entities/renesas-electronics/)
## [ReShape Inc](https://semiengineering.com/entities/reshape-inc/)
## [RevoSys Inc.](https://semiengineering.com/entities/revosys-inc/)
## [Right Track CAD Corp.](https://semiengineering.com/entities/right-track-cad-corp/)
## [Rio Design Automation](https://semiengineering.com/entities/rio-design-automation/)
## [Riscure](https://semiengineering.com/entities/riscure/)
## [RivieraWaves](https://semiengineering.com/entities/rivierawaves/)
## [Rocketick](https://semiengineering.com/entities/rocketick/)
## [Router Soutions, Inc.](https://semiengineering.com/entities/router-soutions-inc/)
## [Royal Digital Centers, Inc.](https://semiengineering.com/entities/royal-digital-centers-inc/)
## [RSoft Design Group Inc.](https://semiengineering.com/entities/rsoft-design-group-inc/)
## [Runtime Design Automation](https://semiengineering.com/entities/runtime-design-automation/)
## [S2C Inc.](https://semiengineering.com/entities/s2c-inc/)
## [S3 Group](https://semiengineering.com/entities/s3-group/)
## [Sabio Labs](https://semiengineering.com/entities/sabio-labs/)
## [Safelogic](https://semiengineering.com/entities/safelogic/)
## [Sagantec](https://semiengineering.com/entities/sagantec/)
## [Sage Design Automation, Inc.](https://semiengineering.com/entities/sage-design-automation-inc/)
## [Samsung Semiconductor](https://semiengineering.com/entities/samsung-foundry/)
## [Sand Microelectronics](https://semiengineering.com/entities/sand-microelectronics/)
## [Sandburst](https://semiengineering.com/entities/sandburst/)
## [Sandwork Design, Inc.](https://semiengineering.com/entities/sandwork-design-inc/)
## [Sankalp Semiconductor](https://semiengineering.com/entities/sankalp-semiconductor/)
## [SCALD Corporation](https://semiengineering.com/entities/scald-corporation/)
## [SciFace Software GmbH & Co. KG](https://semiengineering.com/entities/sciface-software-gmbh-co-kg/)
## [SDA Systems Inc.](https://semiengineering.com/entities/sda-systems-inc/)
## [Sedco](https://semiengineering.com/entities/sedco/)
## [See Technologies](https://semiengineering.com/entities/see-technologies/)
## [Seed Solutions Inc.](https://semiengineering.com/entities/seed-solutions-inc/)
## [SEMI](https://semiengineering.com/entities/semi/)
## [Semiconductor Manufacturing International Corp.](https://semiengineering.com/entities/semiconductor-manufacturing-international-corp/)
## [Semifore, Inc.](https://semiengineering.com/entities/semifore-inc/)
## [Sente Inc.](https://semiengineering.com/entities/sente-inc/)
## [Sequence Design](https://semiengineering.com/entities/sequence-design/)
## [SETO Software GmbH](https://semiengineering.com/entities/seto-software-gmbh/)
## [Shiva Multisystems Corp.](https://semiengineering.com/entities/shiva-multisystems-corp/)
## [Si2](https://semiengineering.com/entities/si2/)
## [Si2 Open3D Technical Advisory Board](https://semiengineering.com/entities/si2-open3d-technical-advisory-board/)
## [Sibridge Technologies](https://semiengineering.com/entities/sibridge-technologies/)
## [SiCAD Inc.](https://semiengineering.com/entities/sicad-inc/)
## [Sidense Corp.](https://semiengineering.com/entities/sidense-corp/)
## [Siemens EDA](https://semiengineering.com/entities/mentor-a-siemens-business/)
## [Sierra Design Automation](https://semiengineering.com/entities/sierra-design-automation/)
## [Sigma-C Software AG](https://semiengineering.com/entities/sigma-c-software-ag/)
## [Signal Integrity Software, Inc.](https://semiengineering.com/entities/signal-integrity-software-inc/)
## [Signetics Corporation](https://semiengineering.com/entities/signetics-corporation/)
## [Sigrity, Inc.](https://semiengineering.com/entities/sigrity-inc/)
## [SilabTech Pvt Ltd.](https://semiengineering.com/entities/silabtech-pvt-ltd/)
## [Silc Technologies](https://semiengineering.com/entities/silc-technologies/)
## [Silerity Inc](https://semiengineering.com/entities/silerity-inc/)
## [Silexica](https://semiengineering.com/entities/silexica/)
## [Silicon Architects](https://semiengineering.com/entities/silicon-architects/)
## [Silicon Canvas, Inc.](https://semiengineering.com/entities/silicon-canvas-inc/)
## [Silicon Cloud International Pte Ltd](https://semiengineering.com/entities/silicon-cloud-international-pte-ltd/)
## [Silicon Compiler Systems Corp.](https://semiengineering.com/entities/silicon-compiler-systems-corp/)
## [Silicon Compilers Inc.](https://semiengineering.com/entities/silicon-compilers-inc/)
## [Silicon Creations, LLC](https://semiengineering.com/entities/silicon-creations-llc/)
## [Silicon Design Labs](https://semiengineering.com/entities/silicon-design-labs/)
## [Silicon Design Solutions](https://semiengineering.com/entities/silicon-design-solutions/)
## [Silicon Forest Research inc.](https://semiengineering.com/entities/silicon-forest-research-inc/)
## [Silicon Frontline Technology, Inc.](https://semiengineering.com/entities/silicon-frontline-technology-inc/)
## [Silicon Logic Engineering](https://semiengineering.com/entities/silicon-logic-engineering/)
## [Silicon Metrics Corporation](https://semiengineering.com/entities/silicon-metrics-corporation/)
## [Silicon Perspective Corp.](https://semiengineering.com/entities/silicon-perspective-corp/)
## [Silicon Solutions Corporation](https://semiengineering.com/entities/silicon-solutions-corporation/)
## [Silicon Sorcery](https://semiengineering.com/entities/silicon-sorcery/)
## [Silicon Storage Technology, Inc.](https://semiengineering.com/entities/silicon-storage-technology-inc/)
## [Silicon Valley Research](https://semiengineering.com/entities/silicon-valley-research/)
## [Silicon West](https://semiengineering.com/entities/silicon-west/)
## [SiliconBlue Technologies Corporation](https://semiengineering.com/entities/siliconblue-technologies-corporation/)
## [SiliconGate LDA](https://semiengineering.com/entities/silicongate-lda/)
## [Siliconware Precision Industries](https://semiengineering.com/entities/siliconware-precision-industries/)
## [Silvaco, Inc.](https://semiengineering.com/entities/silvaco-inc/)
## [Silvar-Lisco, Inc.](https://semiengineering.com/entities/silvar-lisco-inc/)
## [Simon Software](https://semiengineering.com/entities/simon-software/)
## [Simpleware](https://semiengineering.com/entities/simpleware/)
## [Simplex Solutions](https://semiengineering.com/entities/simplex-solutions/)
## [Simucad Design Automation Inc.](https://semiengineering.com/entities/simucad-design-automation-inc/)
## [Simucad Inc.](https://semiengineering.com/entities/simucad-inc/)
## [Simulation Technologies Corp](https://semiengineering.com/entities/simulation-technologies-corp/)
## [SimuQuest, Inc.](https://semiengineering.com/entities/simuquest-inc/)
## [Simutech Corporation](https://semiengineering.com/entities/simutech-corporation/)
## [SiVerion, Inc.](https://semiengineering.com/entities/siverion-inc/)
## [SkillCAD, Inc.](https://semiengineering.com/entities/skillcad-inc/)
## [SmartDV Technologies](https://semiengineering.com/entities/smartdv-technologies/)
## [Smartech Oy](https://semiengineering.com/entities/smartech-oy/)
## [SmartPlay Technologies](https://semiengineering.com/entities/smartplay-technologies/)
## [SMIC](https://semiengineering.com/entities/smic/)
## [Snaketech](https://semiengineering.com/entities/snaketech/)
## [SOISIC](https://semiengineering.com/entities/soisic/)
## [Soitec](https://semiengineering.com/entities/soitec/)
## [Solido Design Automation Inc.](https://semiengineering.com/entities/solido-design-automation-inc/)
## [Solidware Technologies, Inc.](https://semiengineering.com/entities/solidware-technologies-inc/)
## [Sonic Focus Inc](https://semiengineering.com/entities/sonic-focus-inc/)
## [Sonics, Inc.](https://semiengineering.com/entities/sonics-inc/)
## [Sonnet Software, Inc.](https://semiengineering.com/entities/sonnet-software-inc/)
## [Space Codesign Systems, Inc.](https://semiengineering.com/entities/space-codesign-systems-inc/)
## [Spectrum Services](https://semiengineering.com/entities/spectrum-services/)
## [Speedgate Inc.](https://semiengineering.com/entities/speedgate-inc/)
## [SpeedSim Inc.](https://semiengineering.com/entities/speedsim-inc/)
## [SpinCircuit Inc](https://semiengineering.com/entities/spincircuit-inc/)
## [SpiraTech Limited](https://semiengineering.com/entities/spiratech-limited/)
## [SPIRIT Consortium](https://semiengineering.com/entities/spirit-consortium/)
## [Springsoft](https://semiengineering.com/entities/springsoft/)
## [SRF Technologies, LLC](https://semiengineering.com/entities/srf-technologies-llc/)
## [STAAR Corporation](https://semiengineering.com/entities/staar-corporation/)
## [Stanford University](https://semiengineering.com/entities/stanford-university/)
## [Stanza Systems, Inc.](https://semiengineering.com/entities/stanza-systems-inc/)
## [STATS ChipPAC](https://semiengineering.com/entities/stats-chippac/)
## [STATS ChipPAC](https://semiengineering.com/entities/stats-chippac-2/)
## [Stelar Tools LLC](https://semiengineering.com/entities/stelar-tools-llc/)
## [STMicroelectronics](https://semiengineering.com/entities/stmicroelectronics/)
## [Summit Design](https://semiengineering.com/entities/summit-design/)
## [Summit Design (new)](https://semiengineering.com/entities/summit-design-new/)
## [Sunrise Test Systems, Inc.](https://semiengineering.com/entities/sunrise-test-systems-inc/)
## [sureCore Ltd](https://semiengineering.com/entities/surecore-ltd/)
## [Surefire Verification Inc.](https://semiengineering.com/entities/surefire-verification-inc/)
## [Swanson Analysis Systems, Inc.](https://semiengineering.com/entities/swanson-analysis-systems-inc/)
## [SwitchCore AB](https://semiengineering.com/entities/switchcore-ab/)
## [Sycon Design](https://semiengineering.com/entities/sycon-design/)
## [Symbionics Group Ltd.](https://semiengineering.com/entities/symbionics-group-ltd/)
## [Symica, LLC](https://semiengineering.com/entities/symica-llc/)
## [Synapse Design Automation Inc.](https://semiengineering.com/entities/synapse-design-automation-inc/)
## [Synaptics](https://semiengineering.com/entities/synaptics/)
## [Synchronous Design Automation](https://semiengineering.com/entities/synchronous-design-automation/)
## [Synergy DataWorks](https://semiengineering.com/entities/synergy-dataworks/)
## [Synfora, Inc.](https://semiengineering.com/entities/synfora-inc/)
## [Synopsys Optical Solutions](https://semiengineering.com/entities/synopsys-optical-solutions/)
## [Synopsys Silicon Library Business](https://semiengineering.com/entities/synopsys-silicon-library-business/)
## [Synopsys, Inc.](https://semiengineering.com/entities/synopsys-inc/)
## [Synplicity, Inc.](https://semiengineering.com/entities/synplicity-inc/)
## [Synthesia AB](https://semiengineering.com/entities/synthesia-ab/)
## [SysChip Design Technologies](https://semiengineering.com/entities/syschip-design-technologies/)
## [Systems & Networks, Inc.](https://semiengineering.com/entities/systems-networks-inc/)
## [Systems Science Inc.](https://semiengineering.com/entities/systems-science-inc/)
## [Systems Science, Inc.](https://semiengineering.com/entities/systems-science-inc-2/)
## [Systolic Technology Ltd.](https://semiengineering.com/entities/systolic-technology-ltd/)
## [Tabulating Machine Company](https://semiengineering.com/entities/tabulating-machine-company/)
## [Tality Corp](https://semiengineering.com/entities/tality-corp/)
## [Tangent Systems Corporation](https://semiengineering.com/entities/tangent-systems-corporation/)
## [Tanner EDA](https://semiengineering.com/entities/tanner-eda/)
## [Tanner Research, Inc.](https://semiengineering.com/entities/tanner-research-inc/)
## [Taray Inc.](https://semiengineering.com/entities/taray-inc/)
## [Target Compiler Technologies N.V.](https://semiengineering.com/entities/target-compiler-technologies-n-v/)
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## [Tektronix, Inc.](https://semiengineering.com/entities/tektronix-inc/)
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## [Telesis Systems Corp](https://semiengineering.com/entities/telesis-systems-corp/)
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## [Tempus Fugit, Inc.](https://semiengineering.com/entities/tempus-fugit-inc/)
## [Tenison Design Automation](https://semiengineering.com/entities/tenison-design-automation/)
## [Tensilica](https://semiengineering.com/entities/tensilica/)
## [Teradyne Corporation](https://semiengineering.com/entities/teradyne-corporation/)
## [TeraRoute LLC](https://semiengineering.com/entities/teraroute-llc/)
## [Test and Verification Solutions Limited](https://semiengineering.com/entities/test-and-verification-solutions-limited/)
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## [Tharas Systems, Inc.](https://semiengineering.com/entities/tharas-systems-inc/)
## [The Silicon Group, Inc.](https://semiengineering.com/entities/the-silicon-group-inc/)
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## [Tiempo](https://semiengineering.com/entities/tiempo/)
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## [TOOL Corporation](https://semiengineering.com/entities/tool-corporation/)
## [Tool-sha Corporation](https://semiengineering.com/entities/tool-sha-corporation/)
## [Tower Semiconductor, Ltd.](https://semiengineering.com/entities/tower-semiconductor-ltd/)
## [TowerJazz](https://semiengineering.com/entities/towerjazz/)
## [Transcendent Design Technology, Inc.](https://semiengineering.com/entities/transcendent-design-technology-inc/)
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## [Translogic Polska sp z o.o.](https://semiengineering.com/entities/translogic-polska-sp-z-o-o/)
## [Transmeta Corporation](https://semiengineering.com/entities/transmeta-corporation/)
## [Transwitch Corp](https://semiengineering.com/entities/transwitch-corp/)
## [TriCN Associates LLC](https://semiengineering.com/entities/tricn-associates-llc/)
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## [Trimeter Technologies](https://semiengineering.com/entities/trimeter-technologies/)
## [TriQuest Design Automation inc.](https://semiengineering.com/entities/triquest-design-automation-inc/)
## [Triscend Corporation](https://semiengineering.com/entities/triscend-corporation/)
## [True Circuits, Inc.](https://semiengineering.com/entities/true-circuits-inc/)
## [Truechip Solutions](https://semiengineering.com/entities/truechip-solutions-pvt-ltd/)
## [TSMC](https://semiengineering.com/entities/tsmc/)
## [TSSI](https://semiengineering.com/entities/tssi/)
## [TTP Communications, PLC](https://semiengineering.com/entities/ttp-communications-plc/)
## [TXOne Networks](https://semiengineering.com/entities/txone-networks/)
## [Ultima Interconnect Technology, Inc.](https://semiengineering.com/entities/ultima-interconnect-technology-inc/)
## [UltraSoC](https://semiengineering.com/entities/ultrasoc/)
## [UMC (United Microelectronics Corporation)](https://semiengineering.com/entities/umc/)
## [UniCAD Inc.](https://semiengineering.com/entities/unicad-inc/)
## [Uniquify, Inc.](https://semiengineering.com/entities/uniquify-inc/)
## [Unisys Corporation](https://semiengineering.com/entities/unisys-corporation/)
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## [Valtrix Systems](https://semiengineering.com/entities/valtrix-systems/)
## [Valydate Inc.](https://semiengineering.com/entities/valydate-inc/)
## [Vantage Analysis Systems, Inc.](https://semiengineering.com/entities/vantage-analysis-systems-inc/)
## [VaST Systems Technology Corporation](https://semiengineering.com/entities/vast-systems-technology-corporation/)
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## [Veeco](https://semiengineering.com/entities/veeco/)
## [Vennsa Technologies](https://semiengineering.com/entities/vennsa-technologies/)
## [VeraTest, Inc.](https://semiengineering.com/entities/veratest-inc/)
## [Veribest](https://semiengineering.com/entities/veribest/)
## [Veridae Systems Inc.](https://semiengineering.com/entities/veridae-systems-inc/)
## [VeriFast Technologies](https://semiengineering.com/entities/verifast-technologies/)
## [Verific Design Automation, Inc.](https://semiengineering.com/entities/verific-design-automation-inc/)
## [Verification IP assets of Qualis](https://semiengineering.com/entities/verification-ip-assets-of-qualis/)
## [Verification Technology Co., Ltd. (Vtech)](https://semiengineering.com/entities/verification-technology-co-ltd/)
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## [Verilux Design Technology](https://semiengineering.com/entities/verilux-design-technology/)
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## [Veritools, Inc.](https://semiengineering.com/entities/veritools-inc/)
## [Verplex Systems Inc.](https://semiengineering.com/entities/verplex-systems-inc/)
## [VeSys Limited](https://semiengineering.com/entities/vesys-limited/)
## [VHDL International](https://semiengineering.com/entities/vhdl-international/)
## [videantis GmbH](https://semiengineering.com/entities/videantis-gmbh/)
## [Video Logic](https://semiengineering.com/entities/video-logic/)
## [Viewlogic PCB/Systems Unit](https://semiengineering.com/entities/viewlogic-pcbsystems-unit/)
## [Viewlogic Systems, Inc.](https://semiengineering.com/entities/viewlogic-systems-inc/)
## [Virage Logic Corporation](https://semiengineering.com/entities/virage-logic-corporation/)
## [VirSim Tool](https://semiengineering.com/entities/virsim-tool/)
## [Virtio Corporation](https://semiengineering.com/entities/virtio-corporation/)
## [Virtual Chips Inc.](https://semiengineering.com/entities/virtual-chips-inc/)
## [Virtual Silicon Technology](https://semiengineering.com/entities/virtual-silicon-technology-inc/)
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## [Vizef Ltd.](https://semiengineering.com/entities/vizef-ltd/)
## [VLAB Works](https://semiengineering.com/entities/vlab-works/)
## [VLSI Technology Inc.](https://semiengineering.com/entities/vlsi-technology-inc/)
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## [Vtool](https://semiengineering.com/entities/vtool/)
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## [Western Digital](https://semiengineering.com/entities/western-digital/)
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## [XCAT Inc.](https://semiengineering.com/entities/xcat-inc/)
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## [Xilinx Inc.](https://semiengineering.com/entities/xilinx-inc/)
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## [Zerosoft Inc.](https://semiengineering.com/entities/zerosoft-inc/)
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## [Zycad System VHDL Unit](https://semiengineering.com/entities/zycad-system-vhdl-unit/)
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