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1. Shard Calculation

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Response:

Calculated Shard: 152 (from laksa152)

2. Crawled Status Check

Query:

curl -X POST \
  'http://laksa152.int.ahrefs:8124/' \
  -H 'Content-Type: text/plain' \
  -H 'X-ClickHouse-Database: crawler3' \
  -H 'Authorization: Basic YXBpOg==' \
  -d 'SELECT getAhrefsURLFromUnparsed(src_unparsed) AS found_url, ifNull(toUnixTimestamp(download_stamp), 0) AS crawl_time, ifNull(toUnixTimestamp(props_url_first_seen), 0) AS first_indexed_time, download_http_code AS http_code, src_unparsed AS src_unparsed, src_root_hash AS src_root_hash, history_drop_reason AS history_drop_reason, meta_title AS meta_title, meta_descriptions AS meta_descriptions, attrs_boilerpipe_text AS attrs_boilerpipe_text, attrs_markdown AS attrs_markdown, attrs_readable_markdown AS attrs_readable_markdown, meta_canonical AS meta_canonical FROM crawler3.page_info_local FINAL PREWHERE (src_root_hash, src_unparsed) IN ((getAhrefsRootHashFromUnparsed(getAhrefsUnparsedNoserviceFromURL(\'https://en.wikipedia.org/wiki/Binary_multiplier\')), getAhrefsUnparsedNoserviceFromURL(\'https://en.wikipedia.org/wiki/Binary_multiplier\'))) FORMAT JSONEachRow'

Response:

{"found_url":"https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier","crawl_time":1774473556,"first_indexed_time":1435760052,"http_code":200,"src_unparsed":"org,wikipedia!en,\/wiki\/Binary_multiplier s443","src_root_hash":"17790707453426894952","history_drop_reason":null,"meta_title":"Binary multiplier - Wikipedia","meta_descriptions":[],"attrs_boilerpipe_text":"From Wikipedia, the free encyclopedia\nA\nbinary multiplier\nis an\nelectronic circuit\nused in\ndigital electronics\n, such as a\ncomputer\n, to\nmultiply\ntwo\nbinary numbers\n.\nA variety of\ncomputer arithmetic\ntechniques can be used to implement a digital multiplier. Most techniques involve computing the set of\npartial products,\nwhich are then summed together using\nbinary adders\n. This process is similar to\nlong multiplication\n, except that it uses a base-2 (\nbinary\n)\nnumeral system\n.\nBetween 1947 and 1949 Arthur Alec Robinson worked for\nEnglish Electric\n, as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early\nMark 1 computer\n.\nHowever, until the late 1970s, most\nminicomputers\ndid not have a multiply instruction, and so programmers used a \"multiply routine\"\n[\n1\n]\n[\n2\n]\n[\n3\n]\nwhich repeatedly\nshifts and accumulates\npartial results,\noften written using\nloop unwinding\n.\nMainframe computers\nhad multiply instructions, but they did the same sorts of shifts and adds as a \"multiply routine\".\nEarly\nmicroprocessors\nalso had no multiply instruction.  Though the multiply instruction became common with the 16-bit generation,\n[\n4\n]\nat least two 8-bit processors have a multiply instruction: the\nMotorola 6809\n, introduced in 1978,\n[\n5\n]\nand\nIntel MCS-51\nfamily, developed in 1980, and later the modern\nAtmel AVR\n8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers.\nAs more\ntransistors per chip\nbecame available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time.\nBecause some common\ndigital signal processing\nalgorithms spend most of their time multiplying,\ndigital signal processor\ndesigners sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle\nmultiply–accumulate\nunit often used up most of the chip area of early DSPs.\nUnsigned integer multiplication\n[\nedit\n]\nBinary long multiplication\n[\nedit\n]\nThe method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9):\n123\n   × 456\n   =====\n     738  (this is 123 × 6)\n    615   (this is 123 × 5, shifted one position to the left)\n + 492    (this is 123 × 4, shifted two positions to the left)\n   =====\n   56088\nA binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number),\nshifting\nthem left, and then adding them together (a binary addition, of course):\n1011   (this is binary for decimal 11)\n     × 1110   (this is binary for decimal 14)\n     ======\n       0000   (this is 1011 × 0)\n      1011    (this is 1011 × 1, shifted one position to the left)\n     1011     (this is 1011 × 1, shifted two positions to the left)\n  + 1011      (this is 1011 × 1, shifted three positions to the left)\n  =========\n   10011010   (this is binary for decimal 154)\nThis is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds.\nThis method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63.\nSuppose we want to multiply two\nunsigned\n8-bit integers together:\na\n[7:0] and\nb\n[7:0]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand\na\n:\np0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0]\n p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0]\n p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0]\n p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0]\n p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0]\n p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0]\n p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0]\n p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0]\nwhere the following\nVerilog\nnotation is used:\n{8{a[0]}} means repeating a[0] (the 0th bit of a) 8 times.\na\n[7:0] stands for the selecting\na\nfrom its 7th bit to its 0th bit, inclusive, for a total of 8 bits.\n&\nsymbol stands for a bitwise AND.\nIn order to obtain our product, we then need to add up all eight of our partial products, as shown here:\np0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0]\n                                       +  p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0]   0\n                                 +  p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0]   0     0\n                           +  p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0]   0     0     0\n                     +  p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0]   0     0     0     0\n               +  p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0]   0     0     0     0     0\n         +  p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0]   0     0     0     0     0     0\n   +  p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0]   0     0     0     0     0     0     0\n-----------------------------------------------------------------------------------------------\nP[15] P[14] P[13] P[12] P[11] P[10]  P[9]  P[8]  P[7]  P[6]  P[5]  P[4]  P[3]  P[2]  P[1]  P[0]\nIn other words,\nP\n[15:0] is produced by summing\np0\n,\np1\n<< 1,\np2\n<< 2, and so forth, to produce our final unsigned 16-bit product:\nP\n[15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7)\nBuilding on top of smaller blocks\n[\nedit\n]\nSuppose we now want to multiply two\nunsigned\n16-bit integers together:\nu\n[15:0] and\nv\n[15:0] using the 8-by-8-bit multiplier from before. Using the\npartial products method\n(justified by the associativity of multiplication) and running in 8-bit chunks, we have:\np0[15:0] = u[7:0] × v[7:0]\np1[15:0] = u[15:8] × v[7:0]\np2[15:0] = u[7:0] × v[15:8]\np3[15:0] = u[15:8] × v[15:8]\nThe final product would then be:\nP[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16\nOne notices that if only P[15:0] (the lower 16 bits of the result) is required, no computation of p3 is needed.\nHardware implementation\n[\nedit\n]\nAs described above, the process of multiplication can be split into 3 steps:\n[\n6\n]\n[\n7\n]\ngenerating partial product\nreducing partial product\ncomputing final product\nOlder multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required.\n[\n8\n]\nModern multiplier architectures use the (modified)\nBaugh–Wooley algorithm\n,\n[\n9\n]\n[\n10\n]\n[\n11\n]\n[\n12\n]\nWallace trees\n, or\nDadda multipliers\nto add the partial products together in a single cycle.\nIn a fast multiplier,\nthe partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier.\n[\n6\n]\nFor speed, the \"reduce partial product\" stages are typically implemented as a\ncarry-save adder\ncomposed of compressors and the \"compute final product\" step is implemented as a fast adder.\nA compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a \"3:2 compressor\": many fast multipliers use such a compressor  implemented in static\nCMOS\n.\nTo achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;\n[\n7\n]\n[\n6\n]\nimplement the compressors in faster logic (such transmission gate logic, pass transistor logic,\ndomino logic\n);\n[\n8\n]\nconnect the compressors in a different pattern; or some combination.\nThe performance of the\nWallace tree\nimplementation is sometimes improved by\nmodified\nBooth encoding\none of the two multiplicands, which reduces the number of partial products that must be summed.\nSingle-cycle multiplier\n[\nedit\n]\nA \"single cycle\" multiplier (or \"fast multiplier\") is pure\ncombinational logic\n.\nSchematic of 2-bit by 2-bit binary multiplier using\nIEEE Std 91\/91a-1991 US symbols\nto implement with two\nXOR gates\nand six\nAND gates\n.\nExtension to other data types\n[\nedit\n]\nIf\nb\nhad been a\nsigned\ninteger instead of an\nunsigned\ninteger, then the partial products would need to have been sign-extended up to the width of the product before summing.  If\na\nhad been a signed integer, then partial product\np7\nwould need to be subtracted from the final sum, rather than added to it.\nThe above array multiplier can be modified to support\ntwo's complement notation\nsigned numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term:\n1   ~p0[7]  p0[6]  p0[5]  p0[4]  p0[3]  p0[2]  p0[1]  p0[0]\n                                              +  ~p1[7]  p1[6]  p1[5]  p1[4]  p1[3]  p1[2]  p1[1]  p1[0]    0\n                                       +  ~p2[7]  p2[6]  p2[5]  p2[4]  p2[3]  p2[2]  p2[1]  p2[0]    0      0\n                                +  ~p3[7]  p3[6]  p3[5]  p3[4]  p3[3]  p3[2]  p3[1]  p3[0]    0      0      0\n                         +  ~p4[7]  p4[6]  p4[5]  p4[4]  p4[3]  p4[2]  p4[1]  p4[0]    0      0      0      0\n                  +  ~p5[7]  p5[6]  p5[5]  p5[4]  p5[3]  p5[2]  p5[1]  p5[0]    0      0      0      0      0\n           +  ~p6[7]  p6[6]  p6[5]  p6[4]  p6[3]  p6[2]  p6[1]  p6[0]    0      0      0      0      0      0\n+  1    p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0]    0      0      0      0      0      0      0\n---------------------------------------------------------------------------------------------------------------\n P[15]  P[14]  P[13]  P[12]  P[11]  P[10]   P[9]   P[8]   P[7]   P[6]   P[5]   P[4]   P[3]   P[2]   P[1]   P[0]\nWhere ~p represents the complement (opposite value) of p.\nThere are many simplifications in the bit array above that are not shown and are not obvious.\nThe sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension.\nThe sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position).\nFor both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB.  When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that \"magically\" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.\n[\n13\n]\nFloating-point numbers\n[\nedit\n]\nA\nbinary floating-point number\ncontains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately.\nBooth's multiplication algorithm\nFused multiply–add\nDadda multiplier\nWallace tree\nBKM algorithm\nfor complex logarithms and exponentials\nKochanski multiplication\nfor\nmodular\nmultiplication\nLogical shift left\n^\nRather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) [1993].\n\"The evolution of Forth\"\n. In Bergin, Thomas J.; Gibson, Richard G. (eds.).\nHistory of programming languages---II\n. Association for Computing Machinery. pp. \n625–\n670.\ndoi\n:\n10.1145\/234286.1057832\n.\nISBN\n \n0201895021\n.\n^\nDavies, A.C.; Fung, Y.T. (1977).\n\"Interfacing a hardware multiplier to a general-purpose microprocessor\"\n.\nMicroprocessors\n.\n1\n(7):\n425–\n432.\ndoi\n:\n10.1016\/0308-5953(77)90004-6\n.\n^\nRafiquzzaman, M.\n(2005).\n\"§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers\"\n.\nFundamentals of Digital Logic and Microcomputer Design\n.\nWiley\n. p. 46.\nISBN\n \n978-0-47173349-2\n.\n^\nRafiquzzaman 2005\n,\n§7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251\n^\nKant, Krishna (2007).\n\"§2.11.2 16-Bit Microprocessors\"\n.\nMicroprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096\n. PHI Learning. p. 57.\nISBN\n \n9788120331914\n.\n^\na\nb\nc\nRouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan.\n\"A New Design for 7:2 Compressors\"\n(PDF)\n.\n^\na\nb\nLeong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick.\n\"Performance Comparison Review of 8-3 compressor on FPGA\"\n.\n^\na\nb\nPeng Chang.\n\"A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design\"\n.\n2008.\n^\nBaugh, Charles Richmond; Wooley, Bruce A. (December 1973). \"A Two's Complement Parallel Array Multiplication Algorithm\".\nIEEE Transactions on Computers\n.\nC-22\n(12):\n1045–\n1047.\ndoi\n:\n10.1109\/T-C.1973.223648\n.\nS2CID\n \n7473784\n.\n^\nHatamian, Mehdi; Cash, Glenn (1986).\n\"A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS\"\n.\nIEEE Journal of Solid-State Circuits\n.\n21\n(4):\n505–\n513.\nBibcode\n:\n1986IJSSC..21..505H\n.\ndoi\n:\n10.1109\/jssc.1986.1052564\n.\n^\nGebali, Fayez (2003).\n\"Baugh–Wooley Multiplier\"\n(PDF)\n.\nUniversity of Victoria\n, CENG 465 Lab 2.\nArchived\n(PDF)\nfrom the original on 2018-04-14\n. Retrieved\n2018-04-14\n.\n^\nReynders, Nele; Dehaene, Wim (2015).\nUltra-Low-Voltage Design of Energy-Efficient Digital Circuits\n. Analog Circuits and Signal Processing. Springer.\ndoi\n:\n10.1007\/978-3-319-16136-5\n.\nISBN\n \n978-3-319-16135-8\n.\nISSN\n \n1872-082X\n.\nLCCN\n \n2015935431\n.\n^\nParhami, Behrooz (2000).\nComputer Arithmetic: Algorithms and Hardware Designs\n.\nOxford University Press\n.\nISBN\n \n0-19-512583-5\n.\nHennessy, John L.; Patterson, David A. (1990). \"Section A.2, section A.9\".\nComputer Architecture: A quantitative Approach\n. Morgan Kaufmann. pp. A–3..A–6, A–39..A–49.\nISBN\n \n978-0-12383872-8\n.\nMultiplier Designs\ntargeted at\nFPGAs\nBinary Multiplier circuit using Half -Adders and digital gates.","attrs_markdown":"[Jump to content](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#bodyContent)\n\nMain menu\n\nMain menu\n\nmove to sidebar\n\nhide\n\nNavigation\n\n- [Main page](https:\/\/en.wikipedia.org\/wiki\/Main_Page \"Visit the main page [z]\")\n- [Contents](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Contents \"Guides to browsing Wikipedia\")\n- [Current events](https:\/\/en.wikipedia.org\/wiki\/Portal:Current_events \"Articles related to current events\")\n- [Random article](https:\/\/en.wikipedia.org\/wiki\/Special:Random \"Visit a randomly selected article [x]\")\n- [About Wikipedia](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:About \"Learn about Wikipedia and how it works\")\n- [Contact us](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Contact_us \"How to contact Wikipedia\")\n\nContribute\n\n- [Help](https:\/\/en.wikipedia.org\/wiki\/Help:Contents \"Guidance on how to use and edit Wikipedia\")\n- [Learn to edit](https:\/\/en.wikipedia.org\/wiki\/Help:Introduction \"Learn how to edit Wikipedia\")\n- [Community portal](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Community_portal \"The hub for editors\")\n- [Recent changes](https:\/\/en.wikipedia.org\/wiki\/Special:RecentChanges \"A list of recent changes to Wikipedia [r]\")\n- [Upload file](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:File_upload_wizard \"Add images or other media for use on Wikipedia\")\n- [Special pages](https:\/\/en.wikipedia.org\/wiki\/Special:SpecialPages \"A list of all special pages [q]\")\n\n[![](https:\/\/en.wikipedia.org\/static\/images\/icons\/enwiki-25.svg) ![Wikipedia](https:\/\/en.wikipedia.org\/static\/images\/mobile\/copyright\/wikipedia-wordmark-en-25.svg) ![The Free Encyclopedia](https:\/\/en.wikipedia.org\/static\/images\/mobile\/copyright\/wikipedia-tagline-en-25.svg)](https:\/\/en.wikipedia.org\/wiki\/Main_Page)\n\n[Search](https:\/\/en.wikipedia.org\/wiki\/Special:Search \"Search Wikipedia [f]\")\n\nAppearance\n\n- [Donate](https:\/\/donate.wikimedia.org\/?wmf_source=donate&wmf_medium=sidebar&wmf_campaign=en.wikipedia.org&uselang=en)\n- [Create account](https:\/\/en.wikipedia.org\/w\/index.php?title=Special:CreateAccount&returnto=Binary+multiplier \"You are encouraged to create an account and log in; however, it is not mandatory\")\n- [Log in](https:\/\/en.wikipedia.org\/w\/index.php?title=Special:UserLogin&returnto=Binary+multiplier \"You're encouraged to log in; however, it's not mandatory. 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[o]\")\n\n## Contents\nmove to sidebar\n\nhide\n\n- [(Top)](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier)\n- [1 History](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#History)\n- [2 Unsigned integer multiplication](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Unsigned_integer_multiplication)\n  Toggle Unsigned integer multiplication subsection\n  - [2\\.1 Binary long multiplication](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Binary_long_multiplication)\n  - [2\\.2 A concrete view](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#A_concrete_view)\n  - [2\\.3 Building on top of smaller blocks](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Building_on_top_of_smaller_blocks)\n- [3 Hardware implementation](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Hardware_implementation)\n  Toggle Hardware implementation subsection\n  - [3\\.1 Shift-add](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Shift-add)\n  - [3\\.2 Modern multipliers](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Modern_multipliers)\n  - [3\\.3 Single-cycle multiplier](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Single-cycle_multiplier)\n- [4 Extension to other data types](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Extension_to_other_data_types)\n  Toggle Extension to other data types subsection\n  - [4\\.1 Signed integers](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Signed_integers)\n  - [4\\.2 Floating-point numbers](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#Floating-point_numbers)\n- [5 See also](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#See_also)\n- [6 References](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#References)\n- [7 External links](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#External_links)\n\nToggle the table of contents\n\n# Binary multiplier\n10 languages\n\n- [العربية](https:\/\/ar.wikipedia.org\/wiki\/%D8%B6%D8%A7%D8%B1%D8%A8_%D8%AB%D9%86%D8%A7%D8%A6%D9%8A \"ضارب ثنائي – Arabic\")\n- [Català](https:\/\/ca.wikipedia.org\/wiki\/Multiplicador_binari \"Multiplicador binari – Catalan\")\n- [Deutsch](https:\/\/de.wikipedia.org\/wiki\/Multiplizierer_\\(Digitaltechnik\\) \"Multiplizierer (Digitaltechnik) – German\")\n- [فارسی](https:\/\/fa.wikipedia.org\/wiki\/%D8%B6%D8%B1%D8%A8%E2%80%8C%DA%A9%D9%86%D9%86%D8%AF%D9%87_%D8%AF%D9%88%D8%AF%D9%88%DB%8C%DB%8C \"ضرب‌کننده دودویی – Persian\")\n- [Français](https:\/\/fr.wikipedia.org\/wiki\/Multiplieur \"Multiplieur – French\")\n- [Bahasa Indonesia](https:\/\/id.wikipedia.org\/wiki\/Pengali_biner \"Pengali biner – Indonesian\")\n- [日本語](https:\/\/ja.wikipedia.org\/wiki\/%E4%B9%97%E7%AE%97%E5%99%A8 \"乗算器 – Japanese\")\n- [한국어](https:\/\/ko.wikipedia.org\/wiki\/%EA%B3%B1%EC%85%88%EA%B8%B0 \"곱셈기 – Korean\")\n- [Norsk nynorsk](https:\/\/nn.wikipedia.org\/wiki\/Bin%C3%A6r_multippel \"Binær multippel – Norwegian Nynorsk\")\n- [中文](https:\/\/zh.wikipedia.org\/wiki\/%E4%B9%98%E6%B3%95%E5%99%A8 \"乘法器 – Chinese\")\n\n[Edit links](https:\/\/www.wikidata.org\/wiki\/Special:EntityPage\/Q1377144#sitelinks-wikipedia \"Edit interlanguage links\")\n\n- [Article](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier \"View the content page [c]\")\n- [Talk](https:\/\/en.wikipedia.org\/wiki\/Talk:Binary_multiplier \"Discuss improvements to the content page [t]\")\n\nEnglish\n\n- [Read](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier)\n- [Edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit \"Edit this page [e]\")\n- [View history](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=history \"Past revisions of this page [h]\")\n\nTools\n\nTools\n\nmove to sidebar\n\nhide\n\nActions\n\n- [Read](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier)\n- [Edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit \"Edit this page [e]\")\n- [View history](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=history)\n\nGeneral\n\n- [What links here](https:\/\/en.wikipedia.org\/wiki\/Special:WhatLinksHere\/Binary_multiplier \"List of all English Wikipedia pages containing links to this page [j]\")\n- [Related changes](https:\/\/en.wikipedia.org\/wiki\/Special:RecentChangesLinked\/Binary_multiplier \"Recent changes in pages linked from this page [k]\")\n- [Upload file](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:File_Upload_Wizard \"Upload files [u]\")\n- [Permanent link](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&oldid=1334945769 \"Permanent link to this revision of this page\")\n- [Page information](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=info \"More information about this page\")\n- [Cite this page](https:\/\/en.wikipedia.org\/w\/index.php?title=Special:CiteThisPage&page=Binary_multiplier&id=1334945769&wpFormIdentifier=titleform \"Information on how to cite this page\")\n- [Get shortened URL](https:\/\/en.wikipedia.org\/w\/index.php?title=Special:UrlShortener&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FBinary_multiplier)\n\nPrint\/export\n\n- [Download as PDF](https:\/\/en.wikipedia.org\/w\/index.php?title=Special:DownloadAsPdf&page=Binary_multiplier&action=show-download-screen \"Download this page as a PDF file\")\n- [Printable version](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&printable=yes \"Printable version of this page [p]\")\n\nIn other projects\n\n- [Wikidata item](https:\/\/www.wikidata.org\/wiki\/Special:EntityPage\/Q1377144 \"Structured data on this page hosted by Wikidata [g]\")\n\nAppearance\n\nmove to sidebar\n\nhide\n\nFrom Wikipedia, the free encyclopedia\n\nElectronic circuit used to multiply binary numbers\n\n|   |\n|---|\n| Part of a series on |\n| Arithmetic logic circuits |\n| Quick navigation |\n| Theory [Binary number](https:\/\/en.wikipedia.org\/wiki\/Binary_number \"Binary number\") [Boolean algebra](https:\/\/en.wikipedia.org\/wiki\/Boolean_algebra \"Boolean algebra\") [Logic gate](https:\/\/en.wikipedia.org\/wiki\/Logic_gate \"Logic gate\") [Ones' complement number](https:\/\/en.wikipedia.org\/wiki\/Ones%27_complement \"Ones' complement\") [Two's complement number](https:\/\/en.wikipedia.org\/wiki\/Two%27s_complement \"Two's complement\") [Signed number representations](https:\/\/en.wikipedia.org\/wiki\/Signed_number_representations \"Signed number representations\") |\n|   |\n| Adder (+) [Adder](https:\/\/en.wikipedia.org\/wiki\/Adder_\\(electronics\\) \"Adder (electronics)\") [Half adder](https:\/\/en.wikipedia.org\/wiki\/Half_adder \"Half adder\") [Full adder](https:\/\/en.wikipedia.org\/wiki\/Full_adder \"Full adder\") [Ripple-carry adder](https:\/\/en.wikipedia.org\/wiki\/Ripple-carry_adder \"Ripple-carry adder\") [Carry-lookahead adder](https:\/\/en.wikipedia.org\/wiki\/Carry-lookahead_adder \"Carry-lookahead adder\") [Brent–Kung adder](https:\/\/en.wikipedia.org\/wiki\/Brent%E2%80%93Kung_adder \"Brent–Kung adder\") [Kogge–Stone adder](https:\/\/en.wikipedia.org\/wiki\/Kogge%E2%80%93Stone_adder \"Kogge–Stone adder\") [Ling adder](https:\/\/en.wikipedia.org\/wiki\/Ling_adder \"Ling adder\") [Carry-save adder](https:\/\/en.wikipedia.org\/wiki\/Carry-save_adder \"Carry-save adder\") [Carry-select adder](https:\/\/en.wikipedia.org\/wiki\/Carry-select_adder \"Carry-select adder\") [Carry-skip adder](https:\/\/en.wikipedia.org\/wiki\/Carry-skip_adder \"Carry-skip adder\") |\n| Adder–subtractor (±) [Adder–subtractor](https:\/\/en.wikipedia.org\/wiki\/Adder%E2%80%93subtractor \"Adder–subtractor\") |\n| Subtractor (−) [Subtractor](https:\/\/en.wikipedia.org\/wiki\/Subtractor \"Subtractor\") [Full subtractor](https:\/\/en.wikipedia.org\/wiki\/Full_subtractor \"Full subtractor\") [Half subtractor](https:\/\/en.wikipedia.org\/wiki\/Half_subtractor \"Half subtractor\") |\n| Multiplier (×) [Binary multiplier]() [Multiplication algorithm](https:\/\/en.wikipedia.org\/wiki\/Multiplication_algorithm \"Multiplication algorithm\") [Booth's multiplication algorithm](https:\/\/en.wikipedia.org\/wiki\/Booth%27s_multiplication_algorithm \"Booth's multiplication algorithm\") [Wallace tree](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\") [Dadda multiplier](https:\/\/en.wikipedia.org\/wiki\/Dadda_multiplier \"Dadda multiplier\") [Booth encoding](https:\/\/en.wikipedia.org\/wiki\/Booth_encoding \"Booth encoding\") |\n| Divider (÷) [Binary Divider](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_Divider&action=edit&redlink=1 \"Binary Divider (page does not exist)\") [Division algorithm](https:\/\/en.wikipedia.org\/wiki\/Division_algorithm \"Division algorithm\") |\n| Bitwise ops [Bitwise operation](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation \"Bitwise operation\") [NOT](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation#NOT \"Bitwise operation\") [AND](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation#AND \"Bitwise operation\") [OR](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation#OR \"Bitwise operation\") [XOR](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation#XOR \"Bitwise operation\") [Bit shifts](https:\/\/en.wikipedia.org\/wiki\/Bitwise_operation#Bit_shifts \"Bitwise operation\") [Bit manipulation](https:\/\/en.wikipedia.org\/wiki\/Bit_manipulation \"Bit manipulation\") |\n| See also [Kochanski multiplication](https:\/\/en.wikipedia.org\/wiki\/Kochanski_multiplication \"Kochanski multiplication\") (exponentiation) [Multiply–accumulate operation](https:\/\/en.wikipedia.org\/wiki\/Multiply%E2%80%93accumulate_operation \"Multiply–accumulate operation\") |\n| Categories [Category:Binary arithmetic](https:\/\/en.wikipedia.org\/wiki\/Category:Binary_arithmetic \"Category:Binary arithmetic\") [Category:Computer arithmetic](https:\/\/en.wikipedia.org\/wiki\/Category:Computer_arithmetic \"Category:Computer arithmetic\") |\n| See also [FPU](https:\/\/en.wikipedia.org\/wiki\/Floating-point_unit \"Floating-point unit\") [GPU](https:\/\/en.wikipedia.org\/wiki\/Graphics_processing_unit \"Graphics processing unit\") [AGU](https:\/\/en.wikipedia.org\/wiki\/Address_generation_unit \"Address generation unit\") [Mechanical calculator](https:\/\/en.wikipedia.org\/wiki\/Mechanical_calculator \"Mechanical calculator\") |\n| [v](https:\/\/en.wikipedia.org\/wiki\/Template:Sidebar_arithmetic_logic_circuits \"Template:Sidebar arithmetic logic circuits\") [t](https:\/\/en.wikipedia.org\/wiki\/Template_talk:Sidebar_arithmetic_logic_circuits \"Template talk:Sidebar arithmetic logic circuits\") [e](https:\/\/en.wikipedia.org\/wiki\/Special:EditPage\/Template:Sidebar_arithmetic_logic_circuits \"Special:EditPage\/Template:Sidebar arithmetic logic circuits\") |\n\nA **binary multiplier** is an [electronic circuit](https:\/\/en.wikipedia.org\/wiki\/Electronic_circuit \"Electronic circuit\") used in [digital electronics](https:\/\/en.wikipedia.org\/wiki\/Digital_electronics \"Digital electronics\"), such as a [computer](https:\/\/en.wikipedia.org\/wiki\/Computer \"Computer\"), to [multiply](https:\/\/en.wikipedia.org\/wiki\/Multiplication \"Multiplication\") two [binary numbers](https:\/\/en.wikipedia.org\/wiki\/Binary_number \"Binary number\").\n\nA variety of [computer arithmetic](https:\/\/en.wikipedia.org\/wiki\/Category:Computer_arithmetic \"Category:Computer arithmetic\") techniques can be used to implement a digital multiplier. Most techniques involve computing the set of *partial products,* which are then summed together using [binary adders](https:\/\/en.wikipedia.org\/wiki\/Binary_adder \"Binary adder\"). This process is similar to [long multiplication](https:\/\/en.wikipedia.org\/wiki\/Long_multiplication \"Long multiplication\"), except that it uses a base-2 ([binary](https:\/\/en.wikipedia.org\/wiki\/Binary_numeral_system \"Binary numeral system\")) [numeral system](https:\/\/en.wikipedia.org\/wiki\/Numeral_system \"Numeral system\").\n\n## History\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=1 \"Edit section: History\")\\]\n\nBetween 1947 and 1949 Arthur Alec Robinson worked for [English Electric](https:\/\/en.wikipedia.org\/wiki\/English_Electric \"English Electric\"), as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early [Mark 1 computer](https:\/\/en.wikipedia.org\/wiki\/Manchester_Mark_1 \"Manchester Mark 1\"). However, until the late 1970s, most [minicomputers](https:\/\/en.wikipedia.org\/wiki\/Minicomputers \"Minicomputers\") did not have a multiply instruction, and so programmers used a \"multiply routine\"[\\[1\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-1)[\\[2\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-2)[\\[3\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-3) which repeatedly [shifts and accumulates](https:\/\/en.wikipedia.org\/wiki\/Multiplication_algorithm#Shift_and_add \"Multiplication algorithm\") partial results, often written using [loop unwinding](https:\/\/en.wikipedia.org\/wiki\/Loop_unwinding \"Loop unwinding\"). [Mainframe computers](https:\/\/en.wikipedia.org\/wiki\/Mainframe_computer \"Mainframe computer\") had multiply instructions, but they did the same sorts of shifts and adds as a \"multiply routine\".\n\nEarly [microprocessors](https:\/\/en.wikipedia.org\/wiki\/Microprocessor \"Microprocessor\") also had no multiply instruction. Though the multiply instruction became common with the 16-bit generation,[\\[4\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-4) at least two 8-bit processors have a multiply instruction: the [Motorola 6809](https:\/\/en.wikipedia.org\/wiki\/Motorola_6809 \"Motorola 6809\"), introduced in 1978,[\\[5\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-5) and [Intel MCS-51](https:\/\/en.wikipedia.org\/wiki\/Intel_MCS-51 \"Intel MCS-51\") family, developed in 1980, and later the modern [Atmel AVR](https:\/\/en.wikipedia.org\/wiki\/Atmel_AVR \"Atmel AVR\") 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers.\n\nAs more [transistors per chip](https:\/\/en.wikipedia.org\/wiki\/Transistor_count \"Transistor count\") became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time.\n\nBecause some common [digital signal processing](https:\/\/en.wikipedia.org\/wiki\/Digital_signal_processing \"Digital signal processing\") algorithms spend most of their time multiplying, [digital signal processor](https:\/\/en.wikipedia.org\/wiki\/Digital_signal_processor \"Digital signal processor\") designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle [multiply–accumulate](https:\/\/en.wikipedia.org\/wiki\/Multiply%E2%80%93accumulate \"Multiply–accumulate\") unit often used up most of the chip area of early DSPs.\n\n## Unsigned integer multiplication\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=2 \"Edit section: Unsigned integer multiplication\")\\]\n\n### Binary long multiplication\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=3 \"Edit section: Binary long multiplication\")\\]\n\nThe method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9):\n```\n     123\n   × 456\n   =====\n     738  (this is 123 × 6)\n    615   (this is 123 × 5, shifted one position to the left)\n + 492    (this is 123 × 4, shifted two positions to the left)\n   =====\n   56088\n```\nA binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), [shifting](https:\/\/en.wikipedia.org\/wiki\/Logical_shift \"Logical shift\") them left, and then adding them together (a binary addition, of course):\n```\n       1011   (this is binary for decimal 11)\n     × 1110   (this is binary for decimal 14)\n     ======\n       0000   (this is 1011 × 0)\n      1011    (this is 1011 × 1, shifted one position to the left)\n     1011     (this is 1011 × 1, shifted two positions to the left)\n  + 1011      (this is 1011 × 1, shifted three positions to the left)\n  =========\n   10011010   (this is binary for decimal 154)\n```\nThis is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds.\n\nThis method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63.\n\n### A concrete view\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=4 \"Edit section: A concrete view\")\\]\n\nSuppose we want to multiply two [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") 8-bit integers together: *a*\\[7:0\\] and *b*\\[7:0\\]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand *a*:\n```\n p0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0]\n p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0]\n p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0]\n p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0]\n p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0]\n p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0]\n p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0]\n p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0]\n```\nwhere the following [Verilog](https:\/\/en.wikipedia.org\/wiki\/Verilog \"Verilog\") notation is used:\n\n- {8{a\\[0\\]}} means repeating a\\[0\\] (the 0th bit of a) 8 times.\n- *a*\\[7:0\\] stands for the selecting *a* from its 7th bit to its 0th bit, inclusive, for a total of 8 bits.\n- `&` symbol stands for a bitwise AND.\n\nIn order to obtain our product, we then need to add up all eight of our partial products, as shown here:\n```\n                                                p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0]\n                                       +  p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0]   0\n                                 +  p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0]   0     0\n                           +  p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0]   0     0     0\n                     +  p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0]   0     0     0     0\n               +  p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0]   0     0     0     0     0\n         +  p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0]   0     0     0     0     0     0\n   +  p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0]   0     0     0     0     0     0     0\n-----------------------------------------------------------------------------------------------\nP[15] P[14] P[13] P[12] P[11] P[10]  P[9]  P[8]  P[7]  P[6]  P[5]  P[4]  P[3]  P[2]  P[1]  P[0]\n```\nIn other words, *P*\\[15:0\\] is produced by summing *p0*, *p1* \\<\\< 1, *p2* \\<\\< 2, and so forth, to produce our final unsigned 16-bit product:\n```\nP[15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7)\n```\n### Building on top of smaller blocks\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=5 \"Edit section: Building on top of smaller blocks\")\\]\n\nSuppose we now want to multiply two [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") 16-bit integers together: *u*\\[15:0\\] and *v*\\[15:0\\] using the 8-by-8-bit multiplier from before. Using the [partial products method](https:\/\/en.wikipedia.org\/wiki\/Partial_products_method \"Partial products method\") (justified by the associativity of multiplication) and running in 8-bit chunks, we have:\n```\np0[15:0] = u[7:0] × v[7:0]\np1[15:0] = u[15:8] × v[7:0]\np2[15:0] = u[7:0] × v[15:8]\np3[15:0] = u[15:8] × v[15:8]\n```\nThe final product would then be:\n```\nP[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16\n```\nOne notices that if only P\\[15:0\\] (the lower 16 bits of the result) is required, no computation of p3 is needed.\n\n## Hardware implementation\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=6 \"Edit section: Hardware implementation\")\\]\n\nAs described above, the process of multiplication can be split into 3 steps:[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6)[\\[7\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-leong-7)\n\n- generating partial product\n- reducing partial product\n- computing final product\n\n### Shift-add\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=7 \"Edit section: Shift-add\")\\]\n\nOlder multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required.[\\[8\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-chang-8)\n\n### Modern multipliers\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=8 \"Edit section: Modern multipliers\")\\]\n\nModern multiplier architectures use the (modified) [Baugh–Wooley algorithm](https:\/\/en.wikipedia.org\/w\/index.php?title=Baugh%E2%80%93Wooley_algorithm&action=edit&redlink=1 \"Baugh–Wooley algorithm (page does not exist)\"),[\\[9\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Baugh-Wooley_1973-9)[\\[10\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Hatamian-Cash_1986-10)[\\[11\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Gebali_2003-11)[\\[12\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-ULVD_2015-12) [Wallace trees](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\"), or [Dadda multipliers](https:\/\/en.wikipedia.org\/wiki\/Dadda_multiplier \"Dadda multiplier\") to add the partial products together in a single cycle.\n\nIn a fast multiplier, the partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier.[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6) For speed, the \"reduce partial product\" stages are typically implemented as a [carry-save adder](https:\/\/en.wikipedia.org\/wiki\/Carry-save_adder \"Carry-save adder\") composed of compressors and the \"compute final product\" step is implemented as a fast adder.\n\nA compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a \"3:2 compressor\": many fast multipliers use such a compressor implemented in static [CMOS](https:\/\/en.wikipedia.org\/wiki\/CMOS \"CMOS\").\n\nTo achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;[\\[7\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-leong-7)[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6) implement the compressors in faster logic (such transmission gate logic, pass transistor logic, [domino logic](https:\/\/en.wikipedia.org\/wiki\/Domino_logic \"Domino logic\"));[\\[8\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-chang-8) connect the compressors in a different pattern; or some combination.\n\nThe performance of the [Wallace tree](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\") implementation is sometimes improved by *modified* [Booth encoding](https:\/\/en.wikipedia.org\/wiki\/Booth_encoding \"Booth encoding\") one of the two multiplicands, which reduces the number of partial products that must be summed.\n\n### Single-cycle multiplier\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=9 \"Edit section: Single-cycle multiplier\")\\]\n\nA \"single cycle\" multiplier (or \"fast multiplier\") is pure [combinational logic](https:\/\/en.wikipedia.org\/wiki\/Combinational_logic \"Combinational logic\").\n\n[![](https:\/\/upload.wikimedia.org\/wikipedia\/commons\/thumb\/3\/34\/Binary_multiplier.svg\/500px-Binary_multiplier.svg.png)](https:\/\/en.wikipedia.org\/wiki\/File:Binary_multiplier.svg)\n\nSchematic of 2-bit by 2-bit binary multiplier using [IEEE Std 91\/91a-1991 US symbols](https:\/\/en.wikipedia.org\/wiki\/Logic_gate \"Logic gate\") to implement with two [XOR gates](https:\/\/en.wikipedia.org\/wiki\/XOR_gate \"XOR gate\") and six [AND gates](https:\/\/en.wikipedia.org\/wiki\/AND_gate \"AND gate\").\n\n## Extension to other data types\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=10 \"Edit section: Extension to other data types\")\\]\n\n### Signed integers\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=11 \"Edit section: Signed integers\")\\]\n\nIf *b* had been a [signed](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") integer instead of an [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If *a* had been a signed integer, then partial product *p7* would need to be subtracted from the final sum, rather than added to it.\n\nThe above array multiplier can be modified to support [two's complement notation](https:\/\/en.wikipedia.org\/wiki\/Two%27s_complement_notation \"Two's complement notation\") signed numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term:\n```\n                                                    1   ~p0[7]  p0[6]  p0[5]  p0[4]  p0[3]  p0[2]  p0[1]  p0[0]\n                                              +  ~p1[7]  p1[6]  p1[5]  p1[4]  p1[3]  p1[2]  p1[1]  p1[0]    0\n                                       +  ~p2[7]  p2[6]  p2[5]  p2[4]  p2[3]  p2[2]  p2[1]  p2[0]    0      0\n                                +  ~p3[7]  p3[6]  p3[5]  p3[4]  p3[3]  p3[2]  p3[1]  p3[0]    0      0      0\n                         +  ~p4[7]  p4[6]  p4[5]  p4[4]  p4[3]  p4[2]  p4[1]  p4[0]    0      0      0      0\n                  +  ~p5[7]  p5[6]  p5[5]  p5[4]  p5[3]  p5[2]  p5[1]  p5[0]    0      0      0      0      0\n           +  ~p6[7]  p6[6]  p6[5]  p6[4]  p6[3]  p6[2]  p6[1]  p6[0]    0      0      0      0      0      0\n+  1    p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0]    0      0      0      0      0      0      0\n---------------------------------------------------------------------------------------------------------------\n P[15]  P[14]  P[13]  P[12]  P[11]  P[10]   P[9]   P[8]   P[7]   P[6]   P[5]   P[4]   P[3]   P[2]   P[1]   P[0]\n```\nWhere ~p represents the complement (opposite value) of p.\n\n|   |   |\n|---|---|\n| ![](https:\/\/upload.wikimedia.org\/wikipedia\/en\/thumb\/f\/f2\/Edit-clear.svg\/40px-Edit-clear.svg.png) | This section may **require [cleanup](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Cleanup \"Wikipedia:Cleanup\")** to meet Wikipedia's [quality standards](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Manual_of_Style \"Wikipedia:Manual of Style\"). The specific problem is: **Should include proof here.** Please help [improve this section](https:\/\/en.wikipedia.org\/wiki\/Special:EditPage\/Binary_multiplier \"Special:EditPage\/Binary multiplier\") if you can. *(December 2025)* *([Learn how and when to remove this message](https:\/\/en.wikipedia.org\/wiki\/Help:Maintenance_template_removal \"Help:Maintenance template removal\"))* |\n\nThere are many simplifications in the bit array above that are not shown and are not obvious.\n\n- The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension.\n- The sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position).\n\nFor both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that \"magically\" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.[\\[13\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-13)\n\n### Floating-point numbers\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=12 \"Edit section: Floating-point numbers\")\\]\n\nA [binary floating-point number](https:\/\/en.wikipedia.org\/wiki\/Binary_floating-point_number \"Binary floating-point number\") contains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately.\n\n## See also\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=13 \"Edit section: See also\")\\]\n\n- [Booth's multiplication algorithm](https:\/\/en.wikipedia.org\/wiki\/Booth%27s_multiplication_algorithm \"Booth's multiplication algorithm\")\n- [Fused multiply–add](https:\/\/en.wikipedia.org\/wiki\/Fused_multiply%E2%80%93add \"Fused multiply–add\")\n- [Dadda multiplier](https:\/\/en.wikipedia.org\/wiki\/Dadda_multiplier \"Dadda multiplier\")\n- [Wallace tree](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\")\n- [BKM algorithm](https:\/\/en.wikipedia.org\/wiki\/BKM_algorithm \"BKM algorithm\") for complex logarithms and exponentials\n- [Kochanski multiplication](https:\/\/en.wikipedia.org\/wiki\/Kochanski_multiplication \"Kochanski multiplication\") for [modular](https:\/\/en.wikipedia.org\/wiki\/Modular_arithmetic \"Modular arithmetic\") multiplication\n- [Logical shift left](https:\/\/en.wikipedia.org\/wiki\/Logical_shift_left \"Logical shift left\")\n\n## References\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=14 \"Edit section: References\")\\]\n\n1. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-1)**\n   Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) \\[1993\\]. [\"The evolution of Forth\"](http:\/\/www.forth.com\/resources\/evolution\/index.html). In Bergin, Thomas J.; Gibson, Richard G. (eds.). *History of programming languages---II*. Association for Computing Machinery. pp. 625–670\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1145\/234286.1057832](https:\/\/doi.org\/10.1145%2F234286.1057832). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [0201895021](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/0201895021 \"Special:BookSources\/0201895021\")\n   \n   .\n2. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-2)**\n   Davies, A.C.; Fung, Y.T. (1977). [\"Interfacing a hardware multiplier to a general-purpose microprocessor\"](https:\/\/dx.doi.org\/10.1016\/0308-5953%2877%2990004-6). *Microprocessors*. **1** (7): 425–432\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1016\/0308-5953(77)90004-6](https:\/\/doi.org\/10.1016%2F0308-5953%2877%2990004-6).\n3. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-3)**\n   [Rafiquzzaman, M.](https:\/\/en.wikipedia.org\/wiki\/Mohamed_Rafiquzzaman \"Mohamed Rafiquzzaman\") (2005). [\"§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers\"](https:\/\/books.google.com\/books?id=1QZEawDm9uAC&pg=PA46). *Fundamentals of Digital Logic and Microcomputer Design*. [Wiley](https:\/\/en.wikipedia.org\/wiki\/John_Wiley_%26_Sons \"John Wiley & Sons\"). p. 46. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [978-0-47173349-2](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-0-47173349-2 \"Special:BookSources\/978-0-47173349-2\")\n   \n   .\n4. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-4)** [Rafiquzzaman 2005](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#CITEREFRafiquzzaman2005), [§7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251](https:\/\/books.google.com\/books?id=1QZEawDm9uAC&pg=PA251)\n5. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-5)**\n   Kant, Krishna (2007). [\"§2.11.2 16-Bit Microprocessors\"](https:\/\/books.google.com\/books?id=P-n3kelycHQC&pg=PA57). *Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096*. PHI Learning. p. 57. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [9788120331914](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/9788120331914 \"Special:BookSources\/9788120331914\")\n   \n   .\n6. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-1) [***c***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-2)\n   Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. [\"A New Design for 7:2 Compressors\"](http:\/\/www.dl.edi-info.ir\/A%20New%20Design%20for%2072%20Compressors.pdf) (PDF).\n7. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-leong_7-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-leong_7-1)\n   Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. [\"Performance Comparison Review of 8-3 compressor on FPGA\"](https:\/\/www.researchgate.net\/publication\/322218557).\n8. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-chang_8-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-chang_8-1)  Peng Chang. [\"A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design\"](https:\/\/scholar.uwindsor.ca\/cgi\/viewcontent.cgi?article=8801&context=etd). 2008.\n9. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Baugh-Wooley_1973_9-0)**\n   Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). \"A Two's Complement Parallel Array Multiplication Algorithm\". *[IEEE Transactions on Computers](https:\/\/en.wikipedia.org\/wiki\/IEEE_Transactions_on_Computers \"IEEE Transactions on Computers\")*. **C-22** (12): 1045–1047\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1109\/T-C.1973.223648](https:\/\/doi.org\/10.1109%2FT-C.1973.223648). [S2CID](https:\/\/en.wikipedia.org\/wiki\/S2CID_\\(identifier\\) \"S2CID (identifier)\") [7473784](https:\/\/api.semanticscholar.org\/CorpusID:7473784).\n10. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Hatamian-Cash_1986_10-0)**\n    Hatamian, Mehdi; Cash, Glenn (1986). [\"A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS\"](https:\/\/www.researchgate.net\/publication\/2981745). *[IEEE Journal of Solid-State Circuits](https:\/\/en.wikipedia.org\/wiki\/IEEE_Journal_of_Solid-State_Circuits \"IEEE Journal of Solid-State Circuits\")*. **21** (4): 505–513\\. [Bibcode](https:\/\/en.wikipedia.org\/wiki\/Bibcode_\\(identifier\\) \"Bibcode (identifier)\"):[1986IJSSC..21..505H](https:\/\/ui.adsabs.harvard.edu\/abs\/1986IJSSC..21..505H). [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1109\/jssc.1986.1052564](https:\/\/doi.org\/10.1109%2Fjssc.1986.1052564).\n11. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Gebali_2003_11-0)**\n    Gebali, Fayez (2003). [\"Baugh–Wooley Multiplier\"](http:\/\/www.ece.uvic.ca\/~fayez\/courses\/ceng465\/lab_465\/project2\/multiplier.pdf) (PDF). [University of Victoria](https:\/\/en.wikipedia.org\/wiki\/University_of_Victoria \"University of Victoria\"), CENG 465 Lab 2. [Archived](https:\/\/web.archive.org\/web\/20180414230734\/http:\/\/www.ece.uvic.ca\/~fayez\/courses\/ceng465\/lab_465\/project2\/multiplier.pdf) (PDF) from the original on 2018-04-14. Retrieved 2018-04-14.\n12. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-ULVD_2015_12-0)**\n    Reynders, Nele; Dehaene, Wim (2015). *Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits*. Analog Circuits and Signal Processing. Springer. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1007\/978-3-319-16136-5](https:\/\/doi.org\/10.1007%2F978-3-319-16136-5). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n    \n    [978-3-319-16135-8](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-3-319-16135-8 \"Special:BookSources\/978-3-319-16135-8\")\n    \n    . [ISSN](https:\/\/en.wikipedia.org\/wiki\/ISSN_\\(identifier\\) \"ISSN (identifier)\") [1872-082X](https:\/\/search.worldcat.org\/issn\/1872-082X). [LCCN](https:\/\/en.wikipedia.org\/wiki\/LCCN_\\(identifier\\) \"LCCN (identifier)\") [2015935431](https:\/\/lccn.loc.gov\/2015935431).\n13. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-13)**\n    Parhami, Behrooz (2000). *Computer Arithmetic: Algorithms and Hardware Designs*. [Oxford University Press](https:\/\/en.wikipedia.org\/wiki\/Oxford_University_Press \"Oxford University Press\"). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n    \n    [0-19-512583-5](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/0-19-512583-5 \"Special:BookSources\/0-19-512583-5\")\n    \n    .\n\n- Hennessy, John L.; Patterson, David A. (1990). \"Section A.2, section A.9\". *Computer Architecture: A quantitative Approach*. Morgan Kaufmann. pp. A–3..A–6, A–39..A–49. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n  \n  [978-0-12383872-8](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-0-12383872-8 \"Special:BookSources\/978-0-12383872-8\")\n  \n  .\n\n## External links\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=15 \"Edit section: External links\")\\]\n\n- [Multiplier Designs](http:\/\/www.andraka.com\/multipli.php) targeted at [FPGAs](https:\/\/en.wikipedia.org\/wiki\/FPGA \"FPGA\")\n- [Binary Multiplier circuit using Half -Adders and digital gates.](http:\/\/www.fullchipdesign.com\/binary_multiplier_digital.htm)\n\n![](https:\/\/en.wikipedia.org\/wiki\/Special:CentralAutoLogin\/start?useformat=desktop&type=1x1&usesul3=1)\n\nRetrieved from \"<https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&oldid=1334945769>\"\n\n[Categories](https:\/\/en.wikipedia.org\/wiki\/Help:Category \"Help:Category\"):\n\n- [Digital circuits](https:\/\/en.wikipedia.org\/wiki\/Category:Digital_circuits \"Category:Digital circuits\")\n- [Arithmetic logic circuits](https:\/\/en.wikipedia.org\/wiki\/Category:Arithmetic_logic_circuits \"Category:Arithmetic logic circuits\")\n- [Binary arithmetic](https:\/\/en.wikipedia.org\/wiki\/Category:Binary_arithmetic \"Category:Binary arithmetic\")\n- [Multiplication](https:\/\/en.wikipedia.org\/wiki\/Category:Multiplication \"Category:Multiplication\")\n\nHidden categories:\n\n- [Articles with short description](https:\/\/en.wikipedia.org\/wiki\/Category:Articles_with_short_description \"Category:Articles with short description\")\n- [Short description matches Wikidata](https:\/\/en.wikipedia.org\/wiki\/Category:Short_description_matches_Wikidata \"Category:Short description matches Wikidata\")\n- [Pages using sidebar with the child parameter](https:\/\/en.wikipedia.org\/wiki\/Category:Pages_using_sidebar_with_the_child_parameter \"Category:Pages using sidebar with the child parameter\")\n- [Articles needing cleanup from December 2025](https:\/\/en.wikipedia.org\/wiki\/Category:Articles_needing_cleanup_from_December_2025 \"Category:Articles needing cleanup from December 2025\")\n- [All pages needing cleanup](https:\/\/en.wikipedia.org\/wiki\/Category:All_pages_needing_cleanup \"Category:All pages needing cleanup\")\n- [Cleanup tagged articles with a reason field from December 2025](https:\/\/en.wikipedia.org\/wiki\/Category:Cleanup_tagged_articles_with_a_reason_field_from_December_2025 \"Category:Cleanup tagged articles with a reason field from December 2025\")\n- [Wikipedia pages needing cleanup from December 2025](https:\/\/en.wikipedia.org\/wiki\/Category:Wikipedia_pages_needing_cleanup_from_December_2025 \"Category:Wikipedia pages needing cleanup from December 2025\")\n\n- This page was last edited on 26 January 2026, at 14:07 (UTC).\n- Text is available under the [Creative Commons Attribution-ShareAlike 4.0 License](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License \"Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License\"); additional terms may apply. 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Wikipedia® is a registered trademark of the [Wikimedia Foundation, Inc.](https:\/\/wikimediafoundation.org\/), a non-profit organization.\n\n- [Privacy policy](https:\/\/foundation.wikimedia.org\/wiki\/Special:MyLanguage\/Policy:Privacy_policy)\n- [About Wikipedia](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:About)\n- [Disclaimers](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:General_disclaimer)\n- [Contact Wikipedia](https:\/\/en.wikipedia.org\/wiki\/Wikipedia:Contact_us)\n- [Legal & safety contacts](https:\/\/foundation.wikimedia.org\/wiki\/Special:MyLanguage\/Legal:Wikimedia_Foundation_Legal_and_Safety_Contact_Information)\n- [Code of Conduct](https:\/\/foundation.wikimedia.org\/wiki\/Special:MyLanguage\/Policy:Universal_Code_of_Conduct)\n- [Developers](https:\/\/developer.wikimedia.org\/)\n- [Statistics](https:\/\/stats.wikimedia.org\/#\/en.wikipedia.org)\n- [Cookie statement](https:\/\/foundation.wikimedia.org\/wiki\/Special:MyLanguage\/Policy:Cookie_statement)\n- [Mobile view](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&mobileaction=toggle_view_mobile)\n\n- [![Wikimedia Foundation](https:\/\/en.wikipedia.org\/static\/images\/footer\/wikimedia.svg)](https:\/\/www.wikimedia.org\/)\n- [![Powered by MediaWiki](https:\/\/en.wikipedia.org\/w\/resources\/assets\/mediawiki_compact.svg)](https:\/\/www.mediawiki.org\/)\n\nSearch\n\nToggle the table of contents\n\nBinary multiplier\n\n10 languages\n\n[Add topic](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier)","attrs_readable_markdown":"From Wikipedia, the free encyclopedia\n\nA **binary multiplier** is an [electronic circuit](https:\/\/en.wikipedia.org\/wiki\/Electronic_circuit \"Electronic circuit\") used in [digital electronics](https:\/\/en.wikipedia.org\/wiki\/Digital_electronics \"Digital electronics\"), such as a [computer](https:\/\/en.wikipedia.org\/wiki\/Computer \"Computer\"), to [multiply](https:\/\/en.wikipedia.org\/wiki\/Multiplication \"Multiplication\") two [binary numbers](https:\/\/en.wikipedia.org\/wiki\/Binary_number \"Binary number\").\n\nA variety of [computer arithmetic](https:\/\/en.wikipedia.org\/wiki\/Category:Computer_arithmetic \"Category:Computer arithmetic\") techniques can be used to implement a digital multiplier. Most techniques involve computing the set of *partial products,* which are then summed together using [binary adders](https:\/\/en.wikipedia.org\/wiki\/Binary_adder \"Binary adder\"). This process is similar to [long multiplication](https:\/\/en.wikipedia.org\/wiki\/Long_multiplication \"Long multiplication\"), except that it uses a base-2 ([binary](https:\/\/en.wikipedia.org\/wiki\/Binary_numeral_system \"Binary numeral system\")) [numeral system](https:\/\/en.wikipedia.org\/wiki\/Numeral_system \"Numeral system\").\n\nBetween 1947 and 1949 Arthur Alec Robinson worked for [English Electric](https:\/\/en.wikipedia.org\/wiki\/English_Electric \"English Electric\"), as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early [Mark 1 computer](https:\/\/en.wikipedia.org\/wiki\/Manchester_Mark_1 \"Manchester Mark 1\"). However, until the late 1970s, most [minicomputers](https:\/\/en.wikipedia.org\/wiki\/Minicomputers \"Minicomputers\") did not have a multiply instruction, and so programmers used a \"multiply routine\"[\\[1\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-1)[\\[2\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-2)[\\[3\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-3) which repeatedly [shifts and accumulates](https:\/\/en.wikipedia.org\/wiki\/Multiplication_algorithm#Shift_and_add \"Multiplication algorithm\") partial results, often written using [loop unwinding](https:\/\/en.wikipedia.org\/wiki\/Loop_unwinding \"Loop unwinding\"). [Mainframe computers](https:\/\/en.wikipedia.org\/wiki\/Mainframe_computer \"Mainframe computer\") had multiply instructions, but they did the same sorts of shifts and adds as a \"multiply routine\".\n\nEarly [microprocessors](https:\/\/en.wikipedia.org\/wiki\/Microprocessor \"Microprocessor\") also had no multiply instruction. Though the multiply instruction became common with the 16-bit generation,[\\[4\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-4) at least two 8-bit processors have a multiply instruction: the [Motorola 6809](https:\/\/en.wikipedia.org\/wiki\/Motorola_6809 \"Motorola 6809\"), introduced in 1978,[\\[5\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-5) and [Intel MCS-51](https:\/\/en.wikipedia.org\/wiki\/Intel_MCS-51 \"Intel MCS-51\") family, developed in 1980, and later the modern [Atmel AVR](https:\/\/en.wikipedia.org\/wiki\/Atmel_AVR \"Atmel AVR\") 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers.\n\nAs more [transistors per chip](https:\/\/en.wikipedia.org\/wiki\/Transistor_count \"Transistor count\") became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time.\n\nBecause some common [digital signal processing](https:\/\/en.wikipedia.org\/wiki\/Digital_signal_processing \"Digital signal processing\") algorithms spend most of their time multiplying, [digital signal processor](https:\/\/en.wikipedia.org\/wiki\/Digital_signal_processor \"Digital signal processor\") designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle [multiply–accumulate](https:\/\/en.wikipedia.org\/wiki\/Multiply%E2%80%93accumulate \"Multiply–accumulate\") unit often used up most of the chip area of early DSPs.\n\n## Unsigned integer multiplication\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=2 \"Edit section: Unsigned integer multiplication\")\\]\n\n### Binary long multiplication\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=3 \"Edit section: Binary long multiplication\")\\]\n\nThe method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9):\n```\n     123\n   × 456\n   =====\n     738  (this is 123 × 6)\n    615   (this is 123 × 5, shifted one position to the left)\n + 492    (this is 123 × 4, shifted two positions to the left)\n   =====\n   56088\n```\nA binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), [shifting](https:\/\/en.wikipedia.org\/wiki\/Logical_shift \"Logical shift\") them left, and then adding them together (a binary addition, of course):\n```\n       1011   (this is binary for decimal 11)\n     × 1110   (this is binary for decimal 14)\n     ======\n       0000   (this is 1011 × 0)\n      1011    (this is 1011 × 1, shifted one position to the left)\n     1011     (this is 1011 × 1, shifted two positions to the left)\n  + 1011      (this is 1011 × 1, shifted three positions to the left)\n  =========\n   10011010   (this is binary for decimal 154)\n```\nThis is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds.\n\nThis method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63.\n\nSuppose we want to multiply two [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") 8-bit integers together: *a*\\[7:0\\] and *b*\\[7:0\\]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand *a*:\n```\n p0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0]\n p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0]\n p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0]\n p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0]\n p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0]\n p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0]\n p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0]\n p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0]\n```\nwhere the following [Verilog](https:\/\/en.wikipedia.org\/wiki\/Verilog \"Verilog\") notation is used:\n\n- {8{a\\[0\\]}} means repeating a\\[0\\] (the 0th bit of a) 8 times.\n- *a*\\[7:0\\] stands for the selecting *a* from its 7th bit to its 0th bit, inclusive, for a total of 8 bits.\n- `&` symbol stands for a bitwise AND.\n\nIn order to obtain our product, we then need to add up all eight of our partial products, as shown here:\n```\n                                                p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0]\n                                       +  p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0]   0\n                                 +  p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0]   0     0\n                           +  p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0]   0     0     0\n                     +  p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0]   0     0     0     0\n               +  p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0]   0     0     0     0     0\n         +  p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0]   0     0     0     0     0     0\n   +  p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0]   0     0     0     0     0     0     0\n-----------------------------------------------------------------------------------------------\nP[15] P[14] P[13] P[12] P[11] P[10]  P[9]  P[8]  P[7]  P[6]  P[5]  P[4]  P[3]  P[2]  P[1]  P[0]\n```\nIn other words, *P*\\[15:0\\] is produced by summing *p0*, *p1* \\<\\< 1, *p2* \\<\\< 2, and so forth, to produce our final unsigned 16-bit product:\n```\nP[15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7)\n```\n### Building on top of smaller blocks\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=5 \"Edit section: Building on top of smaller blocks\")\\]\n\nSuppose we now want to multiply two [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") 16-bit integers together: *u*\\[15:0\\] and *v*\\[15:0\\] using the 8-by-8-bit multiplier from before. Using the [partial products method](https:\/\/en.wikipedia.org\/wiki\/Partial_products_method \"Partial products method\") (justified by the associativity of multiplication) and running in 8-bit chunks, we have:\n```\np0[15:0] = u[7:0] × v[7:0]\np1[15:0] = u[15:8] × v[7:0]\np2[15:0] = u[7:0] × v[15:8]\np3[15:0] = u[15:8] × v[15:8]\n```\nThe final product would then be:\n```\nP[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16\n```\nOne notices that if only P\\[15:0\\] (the lower 16 bits of the result) is required, no computation of p3 is needed.\n\n## Hardware implementation\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=6 \"Edit section: Hardware implementation\")\\]\n\nAs described above, the process of multiplication can be split into 3 steps:[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6)[\\[7\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-leong-7)\n\n- generating partial product\n- reducing partial product\n- computing final product\n\nOlder multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required.[\\[8\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-chang-8)\n\nModern multiplier architectures use the (modified) [Baugh–Wooley algorithm](https:\/\/en.wikipedia.org\/w\/index.php?title=Baugh%E2%80%93Wooley_algorithm&action=edit&redlink=1 \"Baugh–Wooley algorithm (page does not exist)\"),[\\[9\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Baugh-Wooley_1973-9)[\\[10\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Hatamian-Cash_1986-10)[\\[11\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-Gebali_2003-11)[\\[12\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-ULVD_2015-12) [Wallace trees](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\"), or [Dadda multipliers](https:\/\/en.wikipedia.org\/wiki\/Dadda_multiplier \"Dadda multiplier\") to add the partial products together in a single cycle.\n\nIn a fast multiplier, the partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier.[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6) For speed, the \"reduce partial product\" stages are typically implemented as a [carry-save adder](https:\/\/en.wikipedia.org\/wiki\/Carry-save_adder \"Carry-save adder\") composed of compressors and the \"compute final product\" step is implemented as a fast adder.\n\nA compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a \"3:2 compressor\": many fast multipliers use such a compressor implemented in static [CMOS](https:\/\/en.wikipedia.org\/wiki\/CMOS \"CMOS\").\n\nTo achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;[\\[7\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-leong-7)[\\[6\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-rouholamini-6) implement the compressors in faster logic (such transmission gate logic, pass transistor logic, [domino logic](https:\/\/en.wikipedia.org\/wiki\/Domino_logic \"Domino logic\"));[\\[8\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-chang-8) connect the compressors in a different pattern; or some combination.\n\nThe performance of the [Wallace tree](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\") implementation is sometimes improved by *modified* [Booth encoding](https:\/\/en.wikipedia.org\/wiki\/Booth_encoding \"Booth encoding\") one of the two multiplicands, which reduces the number of partial products that must be summed.\n\n### Single-cycle multiplier\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=9 \"Edit section: Single-cycle multiplier\")\\]\n\nA \"single cycle\" multiplier (or \"fast multiplier\") is pure [combinational logic](https:\/\/en.wikipedia.org\/wiki\/Combinational_logic \"Combinational logic\").\n\n[![](https:\/\/upload.wikimedia.org\/wikipedia\/commons\/thumb\/3\/34\/Binary_multiplier.svg\/500px-Binary_multiplier.svg.png)](https:\/\/en.wikipedia.org\/wiki\/File:Binary_multiplier.svg)\n\nSchematic of 2-bit by 2-bit binary multiplier using [IEEE Std 91\/91a-1991 US symbols](https:\/\/en.wikipedia.org\/wiki\/Logic_gate \"Logic gate\") to implement with two [XOR gates](https:\/\/en.wikipedia.org\/wiki\/XOR_gate \"XOR gate\") and six [AND gates](https:\/\/en.wikipedia.org\/wiki\/AND_gate \"AND gate\").\n\n## Extension to other data types\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=10 \"Edit section: Extension to other data types\")\\]\n\nIf *b* had been a [signed](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") integer instead of an [unsigned](https:\/\/en.wikipedia.org\/wiki\/Signedness \"Signedness\") integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If *a* had been a signed integer, then partial product *p7* would need to be subtracted from the final sum, rather than added to it.\n\nThe above array multiplier can be modified to support [two's complement notation](https:\/\/en.wikipedia.org\/wiki\/Two%27s_complement_notation \"Two's complement notation\") signed numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term:\n```\n                                                    1   ~p0[7]  p0[6]  p0[5]  p0[4]  p0[3]  p0[2]  p0[1]  p0[0]\n                                              +  ~p1[7]  p1[6]  p1[5]  p1[4]  p1[3]  p1[2]  p1[1]  p1[0]    0\n                                       +  ~p2[7]  p2[6]  p2[5]  p2[4]  p2[3]  p2[2]  p2[1]  p2[0]    0      0\n                                +  ~p3[7]  p3[6]  p3[5]  p3[4]  p3[3]  p3[2]  p3[1]  p3[0]    0      0      0\n                         +  ~p4[7]  p4[6]  p4[5]  p4[4]  p4[3]  p4[2]  p4[1]  p4[0]    0      0      0      0\n                  +  ~p5[7]  p5[6]  p5[5]  p5[4]  p5[3]  p5[2]  p5[1]  p5[0]    0      0      0      0      0\n           +  ~p6[7]  p6[6]  p6[5]  p6[4]  p6[3]  p6[2]  p6[1]  p6[0]    0      0      0      0      0      0\n+  1    p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0]    0      0      0      0      0      0      0\n---------------------------------------------------------------------------------------------------------------\n P[15]  P[14]  P[13]  P[12]  P[11]  P[10]   P[9]   P[8]   P[7]   P[6]   P[5]   P[4]   P[3]   P[2]   P[1]   P[0]\n```\nWhere ~p represents the complement (opposite value) of p.\n\nThere are many simplifications in the bit array above that are not shown and are not obvious.\n\n- The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension.\n- The sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position).\n\nFor both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that \"magically\" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.[\\[13\\]](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_note-13)\n\n### Floating-point numbers\n\\[[edit](https:\/\/en.wikipedia.org\/w\/index.php?title=Binary_multiplier&action=edit&section=12 \"Edit section: Floating-point numbers\")\\]\n\nA [binary floating-point number](https:\/\/en.wikipedia.org\/wiki\/Binary_floating-point_number \"Binary floating-point number\") contains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately.\n\n- [Booth's multiplication algorithm](https:\/\/en.wikipedia.org\/wiki\/Booth%27s_multiplication_algorithm \"Booth's multiplication algorithm\")\n- [Fused multiply–add](https:\/\/en.wikipedia.org\/wiki\/Fused_multiply%E2%80%93add \"Fused multiply–add\")\n- [Dadda multiplier](https:\/\/en.wikipedia.org\/wiki\/Dadda_multiplier \"Dadda multiplier\")\n- [Wallace tree](https:\/\/en.wikipedia.org\/wiki\/Wallace_tree \"Wallace tree\")\n- [BKM algorithm](https:\/\/en.wikipedia.org\/wiki\/BKM_algorithm \"BKM algorithm\") for complex logarithms and exponentials\n- [Kochanski multiplication](https:\/\/en.wikipedia.org\/wiki\/Kochanski_multiplication \"Kochanski multiplication\") for [modular](https:\/\/en.wikipedia.org\/wiki\/Modular_arithmetic \"Modular arithmetic\") multiplication\n- [Logical shift left](https:\/\/en.wikipedia.org\/wiki\/Logical_shift_left \"Logical shift left\")\n\n1. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-1)**\n   Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) \\[1993\\]. [\"The evolution of Forth\"](http:\/\/www.forth.com\/resources\/evolution\/index.html). In Bergin, Thomas J.; Gibson, Richard G. (eds.). *History of programming languages---II*. Association for Computing Machinery. pp. 625–670\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1145\/234286.1057832](https:\/\/doi.org\/10.1145%2F234286.1057832). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [0201895021](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/0201895021 \"Special:BookSources\/0201895021\")\n   \n   .\n2. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-2)**\n   Davies, A.C.; Fung, Y.T. (1977). [\"Interfacing a hardware multiplier to a general-purpose microprocessor\"](https:\/\/dx.doi.org\/10.1016\/0308-5953%2877%2990004-6). *Microprocessors*. **1** (7): 425–432\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1016\/0308-5953(77)90004-6](https:\/\/doi.org\/10.1016%2F0308-5953%2877%2990004-6).\n3. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-3)**\n   [Rafiquzzaman, M.](https:\/\/en.wikipedia.org\/wiki\/Mohamed_Rafiquzzaman \"Mohamed Rafiquzzaman\") (2005). [\"§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers\"](https:\/\/books.google.com\/books?id=1QZEawDm9uAC&pg=PA46). *Fundamentals of Digital Logic and Microcomputer Design*. [Wiley](https:\/\/en.wikipedia.org\/wiki\/John_Wiley_%26_Sons \"John Wiley & Sons\"). p. 46. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [978-0-47173349-2](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-0-47173349-2 \"Special:BookSources\/978-0-47173349-2\")\n   \n   .\n4. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-4)** [Rafiquzzaman 2005](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#CITEREFRafiquzzaman2005), [§7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251](https:\/\/books.google.com\/books?id=1QZEawDm9uAC&pg=PA251)\n5. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-5)**\n   Kant, Krishna (2007). [\"§2.11.2 16-Bit Microprocessors\"](https:\/\/books.google.com\/books?id=P-n3kelycHQC&pg=PA57). *Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096*. PHI Learning. p. 57. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n   \n   [9788120331914](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/9788120331914 \"Special:BookSources\/9788120331914\")\n   \n   .\n6. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-1) [***c***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-rouholamini_6-2)\n   Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. [\"A New Design for 7:2 Compressors\"](http:\/\/www.dl.edi-info.ir\/A%20New%20Design%20for%2072%20Compressors.pdf) (PDF).\n7. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-leong_7-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-leong_7-1)\n   Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. [\"Performance Comparison Review of 8-3 compressor on FPGA\"](https:\/\/www.researchgate.net\/publication\/322218557).\n8. ^ [***a***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-chang_8-0) [***b***](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-chang_8-1)  Peng Chang. [\"A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design\"](https:\/\/scholar.uwindsor.ca\/cgi\/viewcontent.cgi?article=8801&context=etd). 2008.\n9. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Baugh-Wooley_1973_9-0)**\n   Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). \"A Two's Complement Parallel Array Multiplication Algorithm\". *[IEEE Transactions on Computers](https:\/\/en.wikipedia.org\/wiki\/IEEE_Transactions_on_Computers \"IEEE Transactions on Computers\")*. **C-22** (12): 1045–1047\\. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1109\/T-C.1973.223648](https:\/\/doi.org\/10.1109%2FT-C.1973.223648). [S2CID](https:\/\/en.wikipedia.org\/wiki\/S2CID_\\(identifier\\) \"S2CID (identifier)\") [7473784](https:\/\/api.semanticscholar.org\/CorpusID:7473784).\n10. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Hatamian-Cash_1986_10-0)**\n    Hatamian, Mehdi; Cash, Glenn (1986). [\"A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS\"](https:\/\/www.researchgate.net\/publication\/2981745). *[IEEE Journal of Solid-State Circuits](https:\/\/en.wikipedia.org\/wiki\/IEEE_Journal_of_Solid-State_Circuits \"IEEE Journal of Solid-State Circuits\")*. **21** (4): 505–513\\. [Bibcode](https:\/\/en.wikipedia.org\/wiki\/Bibcode_\\(identifier\\) \"Bibcode (identifier)\"):[1986IJSSC..21..505H](https:\/\/ui.adsabs.harvard.edu\/abs\/1986IJSSC..21..505H). [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1109\/jssc.1986.1052564](https:\/\/doi.org\/10.1109%2Fjssc.1986.1052564).\n11. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-Gebali_2003_11-0)**\n    Gebali, Fayez (2003). [\"Baugh–Wooley Multiplier\"](http:\/\/www.ece.uvic.ca\/~fayez\/courses\/ceng465\/lab_465\/project2\/multiplier.pdf) (PDF). [University of Victoria](https:\/\/en.wikipedia.org\/wiki\/University_of_Victoria \"University of Victoria\"), CENG 465 Lab 2. [Archived](https:\/\/web.archive.org\/web\/20180414230734\/http:\/\/www.ece.uvic.ca\/~fayez\/courses\/ceng465\/lab_465\/project2\/multiplier.pdf) (PDF) from the original on 2018-04-14. Retrieved 2018-04-14.\n12. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-ULVD_2015_12-0)**\n    Reynders, Nele; Dehaene, Wim (2015). *Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits*. Analog Circuits and Signal Processing. Springer. [doi](https:\/\/en.wikipedia.org\/wiki\/Doi_\\(identifier\\) \"Doi (identifier)\"):[10\\.1007\/978-3-319-16136-5](https:\/\/doi.org\/10.1007%2F978-3-319-16136-5). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n    \n    [978-3-319-16135-8](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-3-319-16135-8 \"Special:BookSources\/978-3-319-16135-8\")\n    \n    . [ISSN](https:\/\/en.wikipedia.org\/wiki\/ISSN_\\(identifier\\) \"ISSN (identifier)\") [1872-082X](https:\/\/search.worldcat.org\/issn\/1872-082X). [LCCN](https:\/\/en.wikipedia.org\/wiki\/LCCN_\\(identifier\\) \"LCCN (identifier)\") [2015935431](https:\/\/lccn.loc.gov\/2015935431).\n13. **[^](https:\/\/en.wikipedia.org\/wiki\/Binary_multiplier#cite_ref-13)**\n    Parhami, Behrooz (2000). *Computer Arithmetic: Algorithms and Hardware Designs*. [Oxford University Press](https:\/\/en.wikipedia.org\/wiki\/Oxford_University_Press \"Oxford University Press\"). [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n    \n    [0-19-512583-5](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/0-19-512583-5 \"Special:BookSources\/0-19-512583-5\")\n    \n    .\n\n- Hennessy, John L.; Patterson, David A. (1990). \"Section A.2, section A.9\". *Computer Architecture: A quantitative Approach*. Morgan Kaufmann. pp. A–3..A–6, A–39..A–49. [ISBN](https:\/\/en.wikipedia.org\/wiki\/ISBN_\\(identifier\\) \"ISBN (identifier)\")\n  \n  [978-0-12383872-8](https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-0-12383872-8 \"Special:BookSources\/978-0-12383872-8\")\n  \n  .\n\n- [Multiplier Designs](http:\/\/www.andraka.com\/multipli.php) targeted at [FPGAs](https:\/\/en.wikipedia.org\/wiki\/FPGA \"FPGA\")\n- [Binary Multiplier circuit using Half -Adders and digital gates.](http:\/\/www.fullchipdesign.com\/binary_multiplier_digital.htm)","meta_canonical":null}

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Boilerpipe Text	From Wikipedia, the free encyclopedia A binary multiplier is an electronic circuit used in digital electronics , such as a computer , to multiply two binary numbers . A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing the set of partial products, which are then summed together using binary adders . This process is similar to long multiplication , except that it uses a base-2 ( binary ) numeral system . Between 1947 and 1949 Arthur Alec Robinson worked for English Electric , as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early Mark 1 computer . However, until the late 1970s, most minicomputers did not have a multiply instruction, and so programmers used a "multiply routine" [ 1 ] [ 2 ] [ 3 ] which repeatedly shifts and accumulates partial results, often written using loop unwinding . Mainframe computers had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine". Early microprocessors also had no multiply instruction. Though the multiply instruction became common with the 16-bit generation, [ 4 ] at least two 8-bit processors have a multiply instruction: the Motorola 6809 , introduced in 1978, [ 5 ] and Intel MCS-51 family, developed in 1980, and later the modern Atmel AVR 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers. As more transistors per chip became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time. Because some common digital signal processing algorithms spend most of their time multiplying, digital signal processor designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle multiply–accumulate unit often used up most of the chip area of early DSPs. Unsigned integer multiplication [ edit ] Binary long multiplication [ edit ] The method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9): 123 × 456 ===== 738 (this is 123 × 6) 615 (this is 123 × 5, shifted one position to the left) + 492 (this is 123 × 4, shifted two positions to the left) ===== 56088 A binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), shifting them left, and then adding them together (a binary addition, of course): 1011 (this is binary for decimal 11) × 1110 (this is binary for decimal 14) ====== 0000 (this is 1011 × 0) 1011 (this is 1011 × 1, shifted one position to the left) 1011 (this is 1011 × 1, shifted two positions to the left) + 1011 (this is 1011 × 1, shifted three positions to the left) ========= 10011010 (this is binary for decimal 154) This is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds. This method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63. Suppose we want to multiply two unsigned 8-bit integers together: a [7:0] and b [7:0]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand a : p0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0] p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0] p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0] p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0] p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0] p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0] p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0] p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0] where the following Verilog notation is used: {8{a[0]}} means repeating a[0] (the 0th bit of a) 8 times. a [7:0] stands for the selecting a from its 7th bit to its 0th bit, inclusive, for a total of 8 bits. & symbol stands for a bitwise AND. In order to obtain our product, we then need to add up all eight of our partial products, as shown here: p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0] 0 0 0 0 0 0 0 ----------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] In other words, P [15:0] is produced by summing p0 , p1 << 1, p2 << 2, and so forth, to produce our final unsigned 16-bit product: P [15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7) Building on top of smaller blocks [ edit ] Suppose we now want to multiply two unsigned 16-bit integers together: u [15:0] and v [15:0] using the 8-by-8-bit multiplier from before. Using the partial products method (justified by the associativity of multiplication) and running in 8-bit chunks, we have: p0[15:0] = u[7:0] × v[7:0] p1[15:0] = u[15:8] × v[7:0] p2[15:0] = u[7:0] × v[15:8] p3[15:0] = u[15:8] × v[15:8] The final product would then be: P[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16 One notices that if only P[15:0] (the lower 16 bits of the result) is required, no computation of p3 is needed. Hardware implementation [ edit ] As described above, the process of multiplication can be split into 3 steps: [ 6 ] [ 7 ] generating partial product reducing partial product computing final product Older multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required. [ 8 ] Modern multiplier architectures use the (modified) Baugh–Wooley algorithm , [ 9 ] [ 10 ] [ 11 ] [ 12 ] Wallace trees , or Dadda multipliers to add the partial products together in a single cycle. In a fast multiplier, the partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier. [ 6 ] For speed, the "reduce partial product" stages are typically implemented as a carry-save adder composed of compressors and the "compute final product" step is implemented as a fast adder. A compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a "3:2 compressor": many fast multipliers use such a compressor implemented in static CMOS . To achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors; [ 7 ] [ 6 ] implement the compressors in faster logic (such transmission gate logic, pass transistor logic, domino logic ); [ 8 ] connect the compressors in a different pattern; or some combination. The performance of the Wallace tree implementation is sometimes improved by modified Booth encoding one of the two multiplicands, which reduces the number of partial products that must be summed. Single-cycle multiplier [ edit ] A "single cycle" multiplier (or "fast multiplier") is pure combinational logic . Schematic of 2-bit by 2-bit binary multiplier using IEEE Std 91/91a-1991 US symbols to implement with two XOR gates and six AND gates . Extension to other data types [ edit ] If b had been a signed integer instead of an unsigned integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If a had been a signed integer, then partial product p7 would need to be subtracted from the final sum, rather than added to it. The above array multiplier can be modified to support two's complement notation signed numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term: 1 ~p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + ~p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + ~p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + ~p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + ~p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + ~p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + ~p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + 1 p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0] 0 0 0 0 0 0 0 --------------------------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] Where ~p represents the complement (opposite value) of p. There are many simplifications in the bit array above that are not shown and are not obvious. The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension. The sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position). For both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that "magically" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book. [ 13 ] Floating-point numbers [ edit ] A binary floating-point number contains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately. Booth's multiplication algorithm Fused multiply–add Dadda multiplier Wallace tree BKM algorithm for complex logarithms and exponentials Kochanski multiplication for modular multiplication Logical shift left ^ Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) [1993]. "The evolution of Forth" . In Bergin, Thomas J.; Gibson, Richard G. (eds.). History of programming languages---II . Association for Computing Machinery. pp. 625– 670. doi : 10.1145/234286.1057832 . ISBN 0201895021 . ^ Davies, A.C.; Fung, Y.T. (1977). "Interfacing a hardware multiplier to a general-purpose microprocessor" . Microprocessors . 1 (7): 425– 432. doi : 10.1016/0308-5953(77)90004-6 . ^ Rafiquzzaman, M. (2005). "§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers" . Fundamentals of Digital Logic and Microcomputer Design . Wiley . p. 46. ISBN 978-0-47173349-2 . ^ Rafiquzzaman 2005 , §7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251 ^ Kant, Krishna (2007). "§2.11.2 16-Bit Microprocessors" . Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096 . PHI Learning. p. 57. ISBN 9788120331914 . ^ a b c Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. "A New Design for 7:2 Compressors" (PDF) . ^ a b Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. "Performance Comparison Review of 8-3 compressor on FPGA" . ^ a b Peng Chang. "A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design" . 2008. ^ Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). "A Two's Complement Parallel Array Multiplication Algorithm". IEEE Transactions on Computers . C-22 (12): 1045– 1047. doi : 10.1109/T-C.1973.223648 . S2CID 7473784 . ^ Hatamian, Mehdi; Cash, Glenn (1986). "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS" . IEEE Journal of Solid-State Circuits . 21 (4): 505– 513. Bibcode : 1986IJSSC..21..505H . doi : 10.1109/jssc.1986.1052564 . ^ Gebali, Fayez (2003). "Baugh–Wooley Multiplier" (PDF) . University of Victoria , CENG 465 Lab 2. Archived (PDF) from the original on 2018-04-14 . Retrieved 2018-04-14 . ^ Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits . Analog Circuits and Signal Processing. Springer. doi : 10.1007/978-3-319-16136-5 . ISBN 978-3-319-16135-8 . ISSN 1872-082X . LCCN 2015935431 . ^ Parhami, Behrooz (2000). Computer Arithmetic: Algorithms and Hardware Designs . Oxford University Press . ISBN 0-19-512583-5 . Hennessy, John L.; Patterson, David A. (1990). "Section A.2, section A.9". Computer Architecture: A quantitative Approach . Morgan Kaufmann. pp. A–3..A–6, A–39..A–49. ISBN 978-0-12383872-8 . Multiplier Designs targeted at FPGAs Binary Multiplier circuit using Half -Adders and digital gates.
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[o]") ## Contents move to sidebar hide - [(Top)](https://en.wikipedia.org/wiki/Binary_multiplier) - [1 History](https://en.wikipedia.org/wiki/Binary_multiplier#History) - [2 Unsigned integer multiplication](https://en.wikipedia.org/wiki/Binary_multiplier#Unsigned_integer_multiplication) Toggle Unsigned integer multiplication subsection - [2\.1 Binary long multiplication](https://en.wikipedia.org/wiki/Binary_multiplier#Binary_long_multiplication) - [2\.2 A concrete view](https://en.wikipedia.org/wiki/Binary_multiplier#A_concrete_view) - [2\.3 Building on top of smaller blocks](https://en.wikipedia.org/wiki/Binary_multiplier#Building_on_top_of_smaller_blocks) - [3 Hardware implementation](https://en.wikipedia.org/wiki/Binary_multiplier#Hardware_implementation) Toggle Hardware implementation subsection - [3\.1 Shift-add](https://en.wikipedia.org/wiki/Binary_multiplier#Shift-add) - [3\.2 Modern multipliers](https://en.wikipedia.org/wiki/Binary_multiplier#Modern_multipliers) - [3\.3 Single-cycle multiplier](https://en.wikipedia.org/wiki/Binary_multiplier#Single-cycle_multiplier) - [4 Extension to other data types](https://en.wikipedia.org/wiki/Binary_multiplier#Extension_to_other_data_types) Toggle Extension to other data types subsection - [4\.1 Signed integers](https://en.wikipedia.org/wiki/Binary_multiplier#Signed_integers) - [4\.2 Floating-point numbers](https://en.wikipedia.org/wiki/Binary_multiplier#Floating-point_numbers) - [5 See also](https://en.wikipedia.org/wiki/Binary_multiplier#See_also) - [6 References](https://en.wikipedia.org/wiki/Binary_multiplier#References) - [7 External links](https://en.wikipedia.org/wiki/Binary_multiplier#External_links) Toggle the table of contents # Binary multiplier 10 languages - [العربية](https://ar.wikipedia.org/wiki/%D8%B6%D8%A7%D8%B1%D8%A8_%D8%AB%D9%86%D8%A7%D8%A6%D9%8A "ضارب ثنائي – Arabic") - [Català](https://ca.wikipedia.org/wiki/Multiplicador_binari "Multiplicador binari – Catalan") - [Deutsch](https://de.wikipedia.org/wiki/Multiplizierer_\(Digitaltechnik\) "Multiplizierer (Digitaltechnik) – German") - [فارسی](https://fa.wikipedia.org/wiki/%D8%B6%D8%B1%D8%A8%E2%80%8C%DA%A9%D9%86%D9%86%D8%AF%D9%87_%D8%AF%D9%88%D8%AF%D9%88%DB%8C%DB%8C "ضرب‌کننده دودویی – Persian") - [Français](https://fr.wikipedia.org/wiki/Multiplieur "Multiplieur – French") - [Bahasa Indonesia](https://id.wikipedia.org/wiki/Pengali_biner "Pengali biner – Indonesian") - [日本語](https://ja.wikipedia.org/wiki/%E4%B9%97%E7%AE%97%E5%99%A8 "乗算器 – Japanese") - [한국어](https://ko.wikipedia.org/wiki/%EA%B3%B1%EC%85%88%EA%B8%B0 "곱셈기 – Korean") - [Norsk nynorsk](https://nn.wikipedia.org/wiki/Bin%C3%A6r_multippel "Binær multippel – Norwegian Nynorsk") - [中文](https://zh.wikipedia.org/wiki/%E4%B9%98%E6%B3%95%E5%99%A8 "乘法器 – Chinese") [Edit links](https://www.wikidata.org/wiki/Special:EntityPage/Q1377144#sitelinks-wikipedia "Edit interlanguage links") - [Article](https://en.wikipedia.org/wiki/Binary_multiplier "View the content page [c]") - [Talk](https://en.wikipedia.org/wiki/Talk:Binary_multiplier "Discuss improvements to the content page [t]") English - [Read](https://en.wikipedia.org/wiki/Binary_multiplier) - [Edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit "Edit this page [e]") - [View history](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=history "Past revisions of this page [h]") Tools Tools move to sidebar hide Actions - [Read](https://en.wikipedia.org/wiki/Binary_multiplier) - [Edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit "Edit this page [e]") - [View history](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=history) General - [What links here](https://en.wikipedia.org/wiki/Special:WhatLinksHere/Binary_multiplier "List of all English Wikipedia pages containing links to this page [j]") - [Related changes](https://en.wikipedia.org/wiki/Special:RecentChangesLinked/Binary_multiplier "Recent changes in pages linked from this page [k]") - [Upload file](https://en.wikipedia.org/wiki/Wikipedia:File_Upload_Wizard "Upload files [u]") - [Permanent link](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&oldid=1334945769 "Permanent link to this revision of this page") - [Page information](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=info "More information about this page") - [Cite this page](https://en.wikipedia.org/w/index.php?title=Special:CiteThisPage&page=Binary_multiplier&id=1334945769&wpFormIdentifier=titleform "Information on how to cite this page") - [Get shortened URL](https://en.wikipedia.org/w/index.php?title=Special:UrlShortener&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FBinary_multiplier) Print/export - [Download as PDF](https://en.wikipedia.org/w/index.php?title=Special:DownloadAsPdf&page=Binary_multiplier&action=show-download-screen "Download this page as a PDF file") - [Printable version](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&printable=yes "Printable version of this page [p]") In other projects - [Wikidata item](https://www.wikidata.org/wiki/Special:EntityPage/Q1377144 "Structured data on this page hosted by Wikidata [g]") Appearance move to sidebar hide From Wikipedia, the free encyclopedia Electronic circuit used to multiply binary numbers \| \| \|---\| \| Part of a series on \| \| Arithmetic logic circuits \| \| Quick navigation \| \| Theory [Binary number](https://en.wikipedia.org/wiki/Binary_number "Binary number") [Boolean algebra](https://en.wikipedia.org/wiki/Boolean_algebra "Boolean algebra") [Logic gate](https://en.wikipedia.org/wiki/Logic_gate "Logic gate") [Ones' complement number](https://en.wikipedia.org/wiki/Ones%27_complement "Ones' complement") [Two's complement number](https://en.wikipedia.org/wiki/Two%27s_complement "Two's complement") [Signed number representations](https://en.wikipedia.org/wiki/Signed_number_representations "Signed number representations") \| \| \| \| Adder (+) [Adder](https://en.wikipedia.org/wiki/Adder_\(electronics\) "Adder (electronics)") [Half adder](https://en.wikipedia.org/wiki/Half_adder "Half adder") [Full adder](https://en.wikipedia.org/wiki/Full_adder "Full adder") [Ripple-carry adder](https://en.wikipedia.org/wiki/Ripple-carry_adder "Ripple-carry adder") [Carry-lookahead adder](https://en.wikipedia.org/wiki/Carry-lookahead_adder "Carry-lookahead adder") [Brent–Kung adder](https://en.wikipedia.org/wiki/Brent%E2%80%93Kung_adder "Brent–Kung adder") [Kogge–Stone adder](https://en.wikipedia.org/wiki/Kogge%E2%80%93Stone_adder "Kogge–Stone adder") [Ling adder](https://en.wikipedia.org/wiki/Ling_adder "Ling adder") [Carry-save adder](https://en.wikipedia.org/wiki/Carry-save_adder "Carry-save adder") [Carry-select adder](https://en.wikipedia.org/wiki/Carry-select_adder "Carry-select adder") [Carry-skip adder](https://en.wikipedia.org/wiki/Carry-skip_adder "Carry-skip adder") \| \| Adder–subtractor (±) [Adder–subtractor](https://en.wikipedia.org/wiki/Adder%E2%80%93subtractor "Adder–subtractor") \| \| Subtractor (−) [Subtractor](https://en.wikipedia.org/wiki/Subtractor "Subtractor") [Full subtractor](https://en.wikipedia.org/wiki/Full_subtractor "Full subtractor") [Half subtractor](https://en.wikipedia.org/wiki/Half_subtractor "Half subtractor") \| \| Multiplier (×) [Binary multiplier]() [Multiplication algorithm](https://en.wikipedia.org/wiki/Multiplication_algorithm "Multiplication algorithm") [Booth's multiplication algorithm](https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm "Booth's multiplication algorithm") [Wallace tree](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree") [Dadda multiplier](https://en.wikipedia.org/wiki/Dadda_multiplier "Dadda multiplier") [Booth encoding](https://en.wikipedia.org/wiki/Booth_encoding "Booth encoding") \| \| Divider (÷) [Binary Divider](https://en.wikipedia.org/w/index.php?title=Binary_Divider&action=edit&redlink=1 "Binary Divider (page does not exist)") [Division algorithm](https://en.wikipedia.org/wiki/Division_algorithm "Division algorithm") \| \| Bitwise ops [Bitwise operation](https://en.wikipedia.org/wiki/Bitwise_operation "Bitwise operation") [NOT](https://en.wikipedia.org/wiki/Bitwise_operation#NOT "Bitwise operation") [AND](https://en.wikipedia.org/wiki/Bitwise_operation#AND "Bitwise operation") [OR](https://en.wikipedia.org/wiki/Bitwise_operation#OR "Bitwise operation") [XOR](https://en.wikipedia.org/wiki/Bitwise_operation#XOR "Bitwise operation") [Bit shifts](https://en.wikipedia.org/wiki/Bitwise_operation#Bit_shifts "Bitwise operation") [Bit manipulation](https://en.wikipedia.org/wiki/Bit_manipulation "Bit manipulation") \| \| See also [Kochanski multiplication](https://en.wikipedia.org/wiki/Kochanski_multiplication "Kochanski multiplication") (exponentiation) [Multiply–accumulate operation](https://en.wikipedia.org/wiki/Multiply%E2%80%93accumulate_operation "Multiply–accumulate operation") \| \| Categories [Category:Binary arithmetic](https://en.wikipedia.org/wiki/Category:Binary_arithmetic "Category:Binary arithmetic") [Category:Computer arithmetic](https://en.wikipedia.org/wiki/Category:Computer_arithmetic "Category:Computer arithmetic") \| \| See also [FPU](https://en.wikipedia.org/wiki/Floating-point_unit "Floating-point unit") [GPU](https://en.wikipedia.org/wiki/Graphics_processing_unit "Graphics processing unit") [AGU](https://en.wikipedia.org/wiki/Address_generation_unit "Address generation unit") [Mechanical calculator](https://en.wikipedia.org/wiki/Mechanical_calculator "Mechanical calculator") \| \| [v](https://en.wikipedia.org/wiki/Template:Sidebar_arithmetic_logic_circuits "Template:Sidebar arithmetic logic circuits") [t](https://en.wikipedia.org/wiki/Template_talk:Sidebar_arithmetic_logic_circuits "Template talk:Sidebar arithmetic logic circuits") [e](https://en.wikipedia.org/wiki/Special:EditPage/Template:Sidebar_arithmetic_logic_circuits "Special:EditPage/Template:Sidebar arithmetic logic circuits") \| A binary multiplier is an [electronic circuit](https://en.wikipedia.org/wiki/Electronic_circuit "Electronic circuit") used in [digital electronics](https://en.wikipedia.org/wiki/Digital_electronics "Digital electronics"), such as a [computer](https://en.wikipedia.org/wiki/Computer "Computer"), to [multiply](https://en.wikipedia.org/wiki/Multiplication "Multiplication") two [binary numbers](https://en.wikipedia.org/wiki/Binary_number "Binary number"). A variety of [computer arithmetic](https://en.wikipedia.org/wiki/Category:Computer_arithmetic "Category:Computer arithmetic") techniques can be used to implement a digital multiplier. Most techniques involve computing the set of partial products, which are then summed together using [binary adders](https://en.wikipedia.org/wiki/Binary_adder "Binary adder"). This process is similar to [long multiplication](https://en.wikipedia.org/wiki/Long_multiplication "Long multiplication"), except that it uses a base-2 ([binary](https://en.wikipedia.org/wiki/Binary_numeral_system "Binary numeral system")) [numeral system](https://en.wikipedia.org/wiki/Numeral_system "Numeral system"). ## History \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=1 "Edit section: History")\] Between 1947 and 1949 Arthur Alec Robinson worked for [English Electric](https://en.wikipedia.org/wiki/English_Electric "English Electric"), as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early [Mark 1 computer](https://en.wikipedia.org/wiki/Manchester_Mark_1 "Manchester Mark 1"). However, until the late 1970s, most [minicomputers](https://en.wikipedia.org/wiki/Minicomputers "Minicomputers") did not have a multiply instruction, and so programmers used a "multiply routine"[\[1\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-1)[\[2\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-2)[\[3\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-3) which repeatedly [shifts and accumulates](https://en.wikipedia.org/wiki/Multiplication_algorithm#Shift_and_add "Multiplication algorithm") partial results, often written using [loop unwinding](https://en.wikipedia.org/wiki/Loop_unwinding "Loop unwinding"). [Mainframe computers](https://en.wikipedia.org/wiki/Mainframe_computer "Mainframe computer") had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine". Early [microprocessors](https://en.wikipedia.org/wiki/Microprocessor "Microprocessor") also had no multiply instruction. Though the multiply instruction became common with the 16-bit generation,[\[4\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-4) at least two 8-bit processors have a multiply instruction: the [Motorola 6809](https://en.wikipedia.org/wiki/Motorola_6809 "Motorola 6809"), introduced in 1978,[\[5\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-5) and [Intel MCS-51](https://en.wikipedia.org/wiki/Intel_MCS-51 "Intel MCS-51") family, developed in 1980, and later the modern [Atmel AVR](https://en.wikipedia.org/wiki/Atmel_AVR "Atmel AVR") 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers. As more [transistors per chip](https://en.wikipedia.org/wiki/Transistor_count "Transistor count") became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time. Because some common [digital signal processing](https://en.wikipedia.org/wiki/Digital_signal_processing "Digital signal processing") algorithms spend most of their time multiplying, [digital signal processor](https://en.wikipedia.org/wiki/Digital_signal_processor "Digital signal processor") designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle [multiply–accumulate](https://en.wikipedia.org/wiki/Multiply%E2%80%93accumulate "Multiply–accumulate") unit often used up most of the chip area of early DSPs. ## Unsigned integer multiplication \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=2 "Edit section: Unsigned integer multiplication")\] ### Binary long multiplication \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=3 "Edit section: Binary long multiplication")\] The method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9): ``` 123 × 456 ===== 738 (this is 123 × 6) 615 (this is 123 × 5, shifted one position to the left) + 492 (this is 123 × 4, shifted two positions to the left) ===== 56088 ``` A binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), [shifting](https://en.wikipedia.org/wiki/Logical_shift "Logical shift") them left, and then adding them together (a binary addition, of course): ``` 1011 (this is binary for decimal 11) × 1110 (this is binary for decimal 14) ====== 0000 (this is 1011 × 0) 1011 (this is 1011 × 1, shifted one position to the left) 1011 (this is 1011 × 1, shifted two positions to the left) + 1011 (this is 1011 × 1, shifted three positions to the left) ========= 10011010 (this is binary for decimal 154) ``` This is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds. This method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63. ### A concrete view \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=4 "Edit section: A concrete view")\] Suppose we want to multiply two [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") 8-bit integers together: a\[7:0\] and b\[7:0\]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand a: ``` p0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0] p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0] p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0] p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0] p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0] p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0] p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0] p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0] ``` where the following [Verilog](https://en.wikipedia.org/wiki/Verilog "Verilog") notation is used: - {8{a\[0\]}} means repeating a\[0\] (the 0th bit of a) 8 times. - a\[7:0\] stands for the selecting a from its 7th bit to its 0th bit, inclusive, for a total of 8 bits. - `&` symbol stands for a bitwise AND. In order to obtain our product, we then need to add up all eight of our partial products, as shown here: ``` p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0] 0 0 0 0 0 0 0 ----------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] ``` In other words, P\[15:0\] is produced by summing p0, p1 \<\< 1, p2 \<\< 2, and so forth, to produce our final unsigned 16-bit product: ``` P[15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7) ``` ### Building on top of smaller blocks \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=5 "Edit section: Building on top of smaller blocks")\] Suppose we now want to multiply two [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") 16-bit integers together: u\[15:0\] and v\[15:0\] using the 8-by-8-bit multiplier from before. Using the [partial products method](https://en.wikipedia.org/wiki/Partial_products_method "Partial products method") (justified by the associativity of multiplication) and running in 8-bit chunks, we have: ``` p0[15:0] = u[7:0] × v[7:0] p1[15:0] = u[15:8] × v[7:0] p2[15:0] = u[7:0] × v[15:8] p3[15:0] = u[15:8] × v[15:8] ``` The final product would then be: ``` P[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16 ``` One notices that if only P\[15:0\] (the lower 16 bits of the result) is required, no computation of p3 is needed. ## Hardware implementation \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=6 "Edit section: Hardware implementation")\] As described above, the process of multiplication can be split into 3 steps:[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6)[\[7\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-leong-7) - generating partial product - reducing partial product - computing final product ### Shift-add \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=7 "Edit section: Shift-add")\] Older multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required.[\[8\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-chang-8) ### Modern multipliers \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=8 "Edit section: Modern multipliers")\] Modern multiplier architectures use the (modified) [Baugh–Wooley algorithm](https://en.wikipedia.org/w/index.php?title=Baugh%E2%80%93Wooley_algorithm&action=edit&redlink=1 "Baugh–Wooley algorithm (page does not exist)"),[\[9\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Baugh-Wooley_1973-9)[\[10\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Hatamian-Cash_1986-10)[\[11\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Gebali_2003-11)[\[12\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-ULVD_2015-12) [Wallace trees](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree"), or [Dadda multipliers](https://en.wikipedia.org/wiki/Dadda_multiplier "Dadda multiplier") to add the partial products together in a single cycle. In a fast multiplier, the partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier.[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6) For speed, the "reduce partial product" stages are typically implemented as a [carry-save adder](https://en.wikipedia.org/wiki/Carry-save_adder "Carry-save adder") composed of compressors and the "compute final product" step is implemented as a fast adder. A compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a "3:2 compressor": many fast multipliers use such a compressor implemented in static [CMOS](https://en.wikipedia.org/wiki/CMOS "CMOS"). To achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;[\[7\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-leong-7)[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6) implement the compressors in faster logic (such transmission gate logic, pass transistor logic, [domino logic](https://en.wikipedia.org/wiki/Domino_logic "Domino logic"));[\[8\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-chang-8) connect the compressors in a different pattern; or some combination. The performance of the [Wallace tree](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree") implementation is sometimes improved by modified [Booth encoding](https://en.wikipedia.org/wiki/Booth_encoding "Booth encoding") one of the two multiplicands, which reduces the number of partial products that must be summed. ### Single-cycle multiplier \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=9 "Edit section: Single-cycle multiplier")\] A "single cycle" multiplier (or "fast multiplier") is pure [combinational logic](https://en.wikipedia.org/wiki/Combinational_logic "Combinational logic"). [![](https://upload.wikimedia.org/wikipedia/commons/thumb/3/34/Binary_multiplier.svg/500px-Binary_multiplier.svg.png)](https://en.wikipedia.org/wiki/File:Binary_multiplier.svg) Schematic of 2-bit by 2-bit binary multiplier using [IEEE Std 91/91a-1991 US symbols](https://en.wikipedia.org/wiki/Logic_gate "Logic gate") to implement with two [XOR gates](https://en.wikipedia.org/wiki/XOR_gate "XOR gate") and six [AND gates](https://en.wikipedia.org/wiki/AND_gate "AND gate"). ## Extension to other data types \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=10 "Edit section: Extension to other data types")\] ### Signed integers \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=11 "Edit section: Signed integers")\] If b had been a [signed](https://en.wikipedia.org/wiki/Signedness "Signedness") integer instead of an [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If a had been a signed integer, then partial product p7 would need to be subtracted from the final sum, rather than added to it. The above array multiplier can be modified to support [two's complement notation](https://en.wikipedia.org/wiki/Two%27s_complement_notation "Two's complement notation") signed numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term: ``` 1 ~p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + ~p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + ~p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + ~p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + ~p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + ~p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + ~p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + 1 p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0] 0 0 0 0 0 0 0 --------------------------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] ``` Where ~p represents the complement (opposite value) of p. \| \| \| \|---\|---\| \| ![](https://upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/40px-Edit-clear.svg.png) \| This section may require [cleanup](https://en.wikipedia.org/wiki/Wikipedia:Cleanup "Wikipedia:Cleanup") to meet Wikipedia's [quality standards](https://en.wikipedia.org/wiki/Wikipedia:Manual_of_Style "Wikipedia:Manual of Style"). The specific problem is: Should include proof here. Please help [improve this section](https://en.wikipedia.org/wiki/Special:EditPage/Binary_multiplier "Special:EditPage/Binary multiplier") if you can. (December 2025) ([Learn how and when to remove this message](https://en.wikipedia.org/wiki/Help:Maintenance_template_removal "Help:Maintenance template removal")) \| There are many simplifications in the bit array above that are not shown and are not obvious. - The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension. - The sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position). For both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that "magically" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.[\[13\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-13) ### Floating-point numbers \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=12 "Edit section: Floating-point numbers")\] A [binary floating-point number](https://en.wikipedia.org/wiki/Binary_floating-point_number "Binary floating-point number") contains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately. ## See also \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=13 "Edit section: See also")\] - [Booth's multiplication algorithm](https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm "Booth's multiplication algorithm") - [Fused multiply–add](https://en.wikipedia.org/wiki/Fused_multiply%E2%80%93add "Fused multiply–add") - [Dadda multiplier](https://en.wikipedia.org/wiki/Dadda_multiplier "Dadda multiplier") - [Wallace tree](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree") - [BKM algorithm](https://en.wikipedia.org/wiki/BKM_algorithm "BKM algorithm") for complex logarithms and exponentials - [Kochanski multiplication](https://en.wikipedia.org/wiki/Kochanski_multiplication "Kochanski multiplication") for [modular](https://en.wikipedia.org/wiki/Modular_arithmetic "Modular arithmetic") multiplication - [Logical shift left](https://en.wikipedia.org/wiki/Logical_shift_left "Logical shift left") ## References \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=14 "Edit section: References")\] 1. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-1) Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) \[1993\]. ["The evolution of Forth"](http://www.forth.com/resources/evolution/index.html). In Bergin, Thomas J.; Gibson, Richard G. (eds.). History of programming languages---II. Association for Computing Machinery. pp. 625–670\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1145/234286.1057832](https://doi.org/10.1145%2F234286.1057832). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [0201895021](https://en.wikipedia.org/wiki/Special:BookSources/0201895021 "Special:BookSources/0201895021") . 2. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-2) Davies, A.C.; Fung, Y.T. (1977). ["Interfacing a hardware multiplier to a general-purpose microprocessor"](https://dx.doi.org/10.1016/0308-5953%2877%2990004-6). Microprocessors. 1 (7): 425–432\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1016/0308-5953(77)90004-6](https://doi.org/10.1016%2F0308-5953%2877%2990004-6). 3. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-3) [Rafiquzzaman, M.](https://en.wikipedia.org/wiki/Mohamed_Rafiquzzaman "Mohamed Rafiquzzaman") (2005). ["§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers"](https://books.google.com/books?id=1QZEawDm9uAC&pg=PA46). Fundamentals of Digital Logic and Microcomputer Design. [Wiley](https://en.wikipedia.org/wiki/John_Wiley_%26_Sons "John Wiley & Sons"). p. 46. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-0-47173349-2](https://en.wikipedia.org/wiki/Special:BookSources/978-0-47173349-2 "Special:BookSources/978-0-47173349-2") . 4. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-4) [Rafiquzzaman 2005](https://en.wikipedia.org/wiki/Binary_multiplier#CITEREFRafiquzzaman2005), [§7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251](https://books.google.com/books?id=1QZEawDm9uAC&pg=PA251) 5. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-5) Kant, Krishna (2007). ["§2.11.2 16-Bit Microprocessors"](https://books.google.com/books?id=P-n3kelycHQC&pg=PA57). Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096. PHI Learning. p. 57. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [9788120331914](https://en.wikipedia.org/wiki/Special:BookSources/9788120331914 "Special:BookSources/9788120331914") . 6. ^ [*a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-1) [c](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-2) Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. ["A New Design for 7:2 Compressors"](http://www.dl.edi-info.ir/A%20New%20Design%20for%2072%20Compressors.pdf) (PDF). 7. ^ [a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-leong_7-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-leong_7-1) Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. ["Performance Comparison Review of 8-3 compressor on FPGA"](https://www.researchgate.net/publication/322218557). 8. ^ [a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-chang_8-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-chang_8-1) Peng Chang. ["A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design"](https://scholar.uwindsor.ca/cgi/viewcontent.cgi?article=8801&context=etd). 2008. 9. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Baugh-Wooley_1973_9-0)* Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). "A Two's Complement Parallel Array Multiplication Algorithm". [IEEE Transactions on Computers](https://en.wikipedia.org/wiki/IEEE_Transactions_on_Computers "IEEE Transactions on Computers"). C-22 (12): 1045–1047\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1109/T-C.1973.223648](https://doi.org/10.1109%2FT-C.1973.223648). [S2CID](https://en.wikipedia.org/wiki/S2CID_\(identifier\) "S2CID (identifier)") [7473784](https://api.semanticscholar.org/CorpusID:7473784). 10. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Hatamian-Cash_1986_10-0) Hatamian, Mehdi; Cash, Glenn (1986). ["A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS"](https://www.researchgate.net/publication/2981745). [IEEE Journal of Solid-State Circuits](https://en.wikipedia.org/wiki/IEEE_Journal_of_Solid-State_Circuits "IEEE Journal of Solid-State Circuits"). 21 (4): 505–513\. [Bibcode](https://en.wikipedia.org/wiki/Bibcode_\(identifier\) "Bibcode (identifier)"):[1986IJSSC..21..505H](https://ui.adsabs.harvard.edu/abs/1986IJSSC..21..505H). [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1109/jssc.1986.1052564](https://doi.org/10.1109%2Fjssc.1986.1052564). 11. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Gebali_2003_11-0) Gebali, Fayez (2003). ["Baugh–Wooley Multiplier"](http://www.ece.uvic.ca/~fayez/courses/ceng465/lab_465/project2/multiplier.pdf) (PDF). [University of Victoria](https://en.wikipedia.org/wiki/University_of_Victoria "University of Victoria"), CENG 465 Lab 2. [Archived](https://web.archive.org/web/20180414230734/http://www.ece.uvic.ca/~fayez/courses/ceng465/lab_465/project2/multiplier.pdf) (PDF) from the original on 2018-04-14. Retrieved 2018-04-14. 12. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-ULVD_2015_12-0) Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1007/978-3-319-16136-5](https://doi.org/10.1007%2F978-3-319-16136-5). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-3-319-16135-8](https://en.wikipedia.org/wiki/Special:BookSources/978-3-319-16135-8 "Special:BookSources/978-3-319-16135-8") . [ISSN](https://en.wikipedia.org/wiki/ISSN_\(identifier\) "ISSN (identifier)") [1872-082X](https://search.worldcat.org/issn/1872-082X). [LCCN](https://en.wikipedia.org/wiki/LCCN_\(identifier\) "LCCN (identifier)") [2015935431](https://lccn.loc.gov/2015935431). 13. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-13) Parhami, Behrooz (2000). Computer Arithmetic: Algorithms and Hardware Designs. [Oxford University Press](https://en.wikipedia.org/wiki/Oxford_University_Press "Oxford University Press"). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [0-19-512583-5](https://en.wikipedia.org/wiki/Special:BookSources/0-19-512583-5 "Special:BookSources/0-19-512583-5") . - Hennessy, John L.; Patterson, David A. (1990). "Section A.2, section A.9". Computer Architecture: A quantitative Approach. Morgan Kaufmann. pp. A–3..A–6, A–39..A–49. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-0-12383872-8](https://en.wikipedia.org/wiki/Special:BookSources/978-0-12383872-8 "Special:BookSources/978-0-12383872-8") . ## External links \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=15 "Edit section: External links")\] - [Multiplier Designs](http://www.andraka.com/multipli.php) targeted at [FPGAs](https://en.wikipedia.org/wiki/FPGA "FPGA") - [Binary Multiplier circuit using Half -Adders and digital gates.](http://www.fullchipdesign.com/binary_multiplier_digital.htm) ![](https://en.wikipedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=1) Retrieved from "<https://en.wikipedia.org/w/index.php?title=Binary_multiplier&oldid=1334945769>" [Categories](https://en.wikipedia.org/wiki/Help:Category "Help:Category"): - [Digital circuits](https://en.wikipedia.org/wiki/Category:Digital_circuits "Category:Digital circuits") - [Arithmetic logic circuits](https://en.wikipedia.org/wiki/Category:Arithmetic_logic_circuits "Category:Arithmetic logic circuits") - [Binary arithmetic](https://en.wikipedia.org/wiki/Category:Binary_arithmetic "Category:Binary arithmetic") - [Multiplication](https://en.wikipedia.org/wiki/Category:Multiplication "Category:Multiplication") Hidden categories: - [Articles with short description](https://en.wikipedia.org/wiki/Category:Articles_with_short_description "Category:Articles with short description") - [Short description matches Wikidata](https://en.wikipedia.org/wiki/Category:Short_description_matches_Wikidata "Category:Short description matches Wikidata") - [Pages using sidebar with the child parameter](https://en.wikipedia.org/wiki/Category:Pages_using_sidebar_with_the_child_parameter "Category:Pages using sidebar with the child parameter") - [Articles needing cleanup from December 2025](https://en.wikipedia.org/wiki/Category:Articles_needing_cleanup_from_December_2025 "Category:Articles needing cleanup from December 2025") - [All pages needing cleanup](https://en.wikipedia.org/wiki/Category:All_pages_needing_cleanup "Category:All pages needing cleanup") - [Cleanup tagged articles with a reason field from December 2025](https://en.wikipedia.org/wiki/Category:Cleanup_tagged_articles_with_a_reason_field_from_December_2025 "Category:Cleanup tagged articles with a reason field from December 2025") - [Wikipedia pages needing cleanup from December 2025](https://en.wikipedia.org/wiki/Category:Wikipedia_pages_needing_cleanup_from_December_2025 "Category:Wikipedia pages needing cleanup from December 2025") - This page was last edited on 26 January 2026, at 14:07 (UTC). - Text is available under the [Creative Commons Attribution-ShareAlike 4.0 License](https://en.wikipedia.org/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License "Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License"); additional terms may apply. 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Readable Markdown	From Wikipedia, the free encyclopedia A binary multiplier is an [electronic circuit](https://en.wikipedia.org/wiki/Electronic_circuit "Electronic circuit") used in [digital electronics](https://en.wikipedia.org/wiki/Digital_electronics "Digital electronics"), such as a [computer](https://en.wikipedia.org/wiki/Computer "Computer"), to [multiply](https://en.wikipedia.org/wiki/Multiplication "Multiplication") two [binary numbers](https://en.wikipedia.org/wiki/Binary_number "Binary number"). A variety of [computer arithmetic](https://en.wikipedia.org/wiki/Category:Computer_arithmetic "Category:Computer arithmetic") techniques can be used to implement a digital multiplier. Most techniques involve computing the set of partial products, which are then summed together using [binary adders](https://en.wikipedia.org/wiki/Binary_adder "Binary adder"). This process is similar to [long multiplication](https://en.wikipedia.org/wiki/Long_multiplication "Long multiplication"), except that it uses a base-2 ([binary](https://en.wikipedia.org/wiki/Binary_numeral_system "Binary numeral system")) [numeral system](https://en.wikipedia.org/wiki/Numeral_system "Numeral system"). Between 1947 and 1949 Arthur Alec Robinson worked for [English Electric](https://en.wikipedia.org/wiki/English_Electric "English Electric"), as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early [Mark 1 computer](https://en.wikipedia.org/wiki/Manchester_Mark_1 "Manchester Mark 1"). However, until the late 1970s, most [minicomputers](https://en.wikipedia.org/wiki/Minicomputers "Minicomputers") did not have a multiply instruction, and so programmers used a "multiply routine"[\[1\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-1)[\[2\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-2)[\[3\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-3) which repeatedly [shifts and accumulates](https://en.wikipedia.org/wiki/Multiplication_algorithm#Shift_and_add "Multiplication algorithm") partial results, often written using [loop unwinding](https://en.wikipedia.org/wiki/Loop_unwinding "Loop unwinding"). [Mainframe computers](https://en.wikipedia.org/wiki/Mainframe_computer "Mainframe computer") had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine". Early [microprocessors](https://en.wikipedia.org/wiki/Microprocessor "Microprocessor") also had no multiply instruction. Though the multiply instruction became common with the 16-bit generation,[\[4\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-4) at least two 8-bit processors have a multiply instruction: the [Motorola 6809](https://en.wikipedia.org/wiki/Motorola_6809 "Motorola 6809"), introduced in 1978,[\[5\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-5) and [Intel MCS-51](https://en.wikipedia.org/wiki/Intel_MCS-51 "Intel MCS-51") family, developed in 1980, and later the modern [Atmel AVR](https://en.wikipedia.org/wiki/Atmel_AVR "Atmel AVR") 8-bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers. As more [transistors per chip](https://en.wikipedia.org/wiki/Transistor_count "Transistor count") became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time. Because some common [digital signal processing](https://en.wikipedia.org/wiki/Digital_signal_processing "Digital signal processing") algorithms spend most of their time multiplying, [digital signal processor](https://en.wikipedia.org/wiki/Digital_signal_processor "Digital signal processor") designers sacrifice considerable chip area in order to make the multiply as fast as possible; a single-cycle [multiply–accumulate](https://en.wikipedia.org/wiki/Multiply%E2%80%93accumulate "Multiply–accumulate") unit often used up most of the chip area of early DSPs. ## Unsigned integer multiplication \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=2 "Edit section: Unsigned integer multiplication")\] ### Binary long multiplication \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=3 "Edit section: Binary long multiplication")\] The method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together. The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit (from 0 to 9): ``` 123 × 456 ===== 738 (this is 123 × 6) 615 (this is 123 × 5, shifted one position to the left) + 492 (this is 123 × 4, shifted two positions to the left) ===== 56088 ``` A binary computer does exactly the same multiplication as decimal numbers do, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), [shifting](https://en.wikipedia.org/wiki/Logical_shift "Logical shift") them left, and then adding them together (a binary addition, of course): ``` 1011 (this is binary for decimal 11) × 1110 (this is binary for decimal 14) ====== 0000 (this is 1011 × 0) 1011 (this is 1011 × 1, shifted one position to the left) 1011 (this is 1011 × 1, shifted two positions to the left) + 1011 (this is 1011 × 1, shifted three positions to the left) ========= 10011010 (this is binary for decimal 154) ``` This is much simpler than in the decimal system, as there is no table of multiplication to remember: just shifts and adds. This method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit. The method is slow, however, as it involves many intermediate additions. These additions are time-consuming. Faster multipliers may be engineered in order to do fewer additions; a modern processor might implement a dedicated parallel adder for partial products, letting the multiplication of two 64-bit numbers be done with only 6 rounds of additions, rather than 63. Suppose we want to multiply two [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") 8-bit integers together: a\[7:0\] and b\[7:0\]. We can produce eight partial products by performing eight 1-bit multiplications, one for each bit in multiplicand a: ``` p0[7:0] = a[0] × b[7:0] = {8{a[0]}} & b[7:0] p1[7:0] = a[1] × b[7:0] = {8{a[1]}} & b[7:0] p2[7:0] = a[2] × b[7:0] = {8{a[2]}} & b[7:0] p3[7:0] = a[3] × b[7:0] = {8{a[3]}} & b[7:0] p4[7:0] = a[4] × b[7:0] = {8{a[4]}} & b[7:0] p5[7:0] = a[5] × b[7:0] = {8{a[5]}} & b[7:0] p6[7:0] = a[6] × b[7:0] = {8{a[6]}} & b[7:0] p7[7:0] = a[7] × b[7:0] = {8{a[7]}} & b[7:0] ``` where the following [Verilog](https://en.wikipedia.org/wiki/Verilog "Verilog") notation is used: - {8{a\[0\]}} means repeating a\[0\] (the 0th bit of a) 8 times. - a\[7:0\] stands for the selecting a from its 7th bit to its 0th bit, inclusive, for a total of 8 bits. - `&` symbol stands for a bitwise AND. In order to obtain our product, we then need to add up all eight of our partial products, as shown here: ``` p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + p7[7] p7[6] p7[5] p7[4] p7[3] p7[2] p7[1] p7[0] 0 0 0 0 0 0 0 ----------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] ``` In other words, P\[15:0\] is produced by summing p0, p1 \<\< 1, p2 \<\< 2, and so forth, to produce our final unsigned 16-bit product: ``` P[15:0] = p0[7:0] + (p1[7:0] << 1) + (p2[7:0] << 2) + (p3[7:0] << 3) + (p4[7:0] << 4) + (p5[7:0] << 5) + (p6[7:0] << 6) + (p7[7:0] << 7) ``` ### Building on top of smaller blocks \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=5 "Edit section: Building on top of smaller blocks")\] Suppose we now want to multiply two [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") 16-bit integers together: u\[15:0\] and v\[15:0\] using the 8-by-8-bit multiplier from before. Using the [partial products method](https://en.wikipedia.org/wiki/Partial_products_method "Partial products method") (justified by the associativity of multiplication) and running in 8-bit chunks, we have: ``` p0[15:0] = u[7:0] × v[7:0] p1[15:0] = u[15:8] × v[7:0] p2[15:0] = u[7:0] × v[15:8] p3[15:0] = u[15:8] × v[15:8] ``` The final product would then be: ``` P[31:0] = p0 + p1 << 8 + p2 << 8 + p3 << 16 ``` One notices that if only P\[15:0\] (the lower 16 bits of the result) is required, no computation of p3 is needed. ## Hardware implementation \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=6 "Edit section: Hardware implementation")\] As described above, the process of multiplication can be split into 3 steps:[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6)[\[7\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-leong-7) - generating partial product - reducing partial product - computing final product Older multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. To achieve the ability to perform one accumulation per cycle, a fast adder (something faster than ripple-carry) is required.[\[8\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-chang-8) Modern multiplier architectures use the (modified) [Baugh–Wooley algorithm](https://en.wikipedia.org/w/index.php?title=Baugh%E2%80%93Wooley_algorithm&action=edit&redlink=1 "Baugh–Wooley algorithm (page does not exist)"),[\[9\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Baugh-Wooley_1973-9)[\[10\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Hatamian-Cash_1986-10)[\[11\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-Gebali_2003-11)[\[12\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-ULVD_2015-12) [Wallace trees](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree"), or [Dadda multipliers](https://en.wikipedia.org/wiki/Dadda_multiplier "Dadda multiplier") to add the partial products together in a single cycle. In a fast multiplier, the partial-product reduction (i.e. computing partial sums) process usually contributes the most to the delay, power, and area of the multiplier.[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6) For speed, the "reduce partial product" stages are typically implemented as a [carry-save adder](https://en.wikipedia.org/wiki/Carry-save_adder "Carry-save adder") composed of compressors and the "compute final product" step is implemented as a fast adder. A compressor is any device that takes more bits as input than it generates as output. In the context of multiplier engineering, it refers to an adder with carry-in and carry-out. The basic compressor is the full adder, a "3:2 compressor": many fast multipliers use such a compressor implemented in static [CMOS](https://en.wikipedia.org/wiki/CMOS "CMOS"). To achieve better performance in the same area or the same performance in a smaller area, multiplier designs may use higher order compressors such as 7:3 compressors;[\[7\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-leong-7)[\[6\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-rouholamini-6) implement the compressors in faster logic (such transmission gate logic, pass transistor logic, [domino logic](https://en.wikipedia.org/wiki/Domino_logic "Domino logic"));[\[8\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-chang-8) connect the compressors in a different pattern; or some combination. The performance of the [Wallace tree](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree") implementation is sometimes improved by modified [Booth encoding](https://en.wikipedia.org/wiki/Booth_encoding "Booth encoding") one of the two multiplicands, which reduces the number of partial products that must be summed. ### Single-cycle multiplier \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=9 "Edit section: Single-cycle multiplier")\] A "single cycle" multiplier (or "fast multiplier") is pure [combinational logic](https://en.wikipedia.org/wiki/Combinational_logic "Combinational logic"). [![](https://upload.wikimedia.org/wikipedia/commons/thumb/3/34/Binary_multiplier.svg/500px-Binary_multiplier.svg.png)](https://en.wikipedia.org/wiki/File:Binary_multiplier.svg) Schematic of 2-bit by 2-bit binary multiplier using [IEEE Std 91/91a-1991 US symbols](https://en.wikipedia.org/wiki/Logic_gate "Logic gate") to implement with two [XOR gates](https://en.wikipedia.org/wiki/XOR_gate "XOR gate") and six [AND gates](https://en.wikipedia.org/wiki/AND_gate "AND gate"). ## Extension to other data types \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=10 "Edit section: Extension to other data types")\] If b had been a [signed](https://en.wikipedia.org/wiki/Signedness "Signedness") integer instead of an [unsigned](https://en.wikipedia.org/wiki/Signedness "Signedness") integer, then the partial products would need to have been sign-extended up to the width of the product before summing. If a had been a signed integer, then partial product p7 would need to be subtracted from the final sum, rather than added to it. The above array multiplier can be modified to support [two's complement notation](https://en.wikipedia.org/wiki/Two%27s_complement_notation "Two's complement notation") signed numbers by inverting several of the product terms and inserting a one to the left of the first and last partial product term: ``` 1 ~p0[7] p0[6] p0[5] p0[4] p0[3] p0[2] p0[1] p0[0] + ~p1[7] p1[6] p1[5] p1[4] p1[3] p1[2] p1[1] p1[0] 0 + ~p2[7] p2[6] p2[5] p2[4] p2[3] p2[2] p2[1] p2[0] 0 0 + ~p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] p3[1] p3[0] 0 0 0 + ~p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] 0 0 0 0 + ~p5[7] p5[6] p5[5] p5[4] p5[3] p5[2] p5[1] p5[0] 0 0 0 0 0 + ~p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] 0 0 0 0 0 0 + 1 p7[7] ~p7[6] ~p7[5] ~p7[4] ~p7[3] ~p7[2] ~p7[1] ~p7[0] 0 0 0 0 0 0 0 --------------------------------------------------------------------------------------------------------------- P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] ``` Where ~p represents the complement (opposite value) of p. There are many simplifications in the bit array above that are not shown and are not obvious. - The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension. - The sequence of p7 (noncomplemented bit followed by all complemented bits) is because we're subtracting this term so they were all negated to start out with (and a 1 was added in the least significant position). For both types of sequences, the last bit is flipped and an implicit −1 should be added directly below the MSB. When the +1 from the two's complement negation for p7 in bit position 0 (LSB) and all the −1's in bit columns 7 through 14 (where each of the MSBs are located) are added together, they can be simplified to the single 1 that "magically" is floating out to the left. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book.[\[13\]](https://en.wikipedia.org/wiki/Binary_multiplier#cite_note-13) ### Floating-point numbers \[[edit](https://en.wikipedia.org/w/index.php?title=Binary_multiplier&action=edit&section=12 "Edit section: Floating-point numbers")\] A [binary floating-point number](https://en.wikipedia.org/wiki/Binary_floating-point_number "Binary floating-point number") contains a sign bit, significant bits (known as the significand) and exponent bits (for simplicity, we don't consider base and combination field). The sign bits of each operand are XOR'd to get the sign of the answer. Then, the two exponents are added to get the exponent of the result. Finally, multiplication of each operand's significand will return the significand of the result. However, if the result of the binary multiplication is higher than the total number of bits for a specific precision (e.g. 32, 64, 128), rounding is required and the exponent is changed appropriately. - [Booth's multiplication algorithm](https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm "Booth's multiplication algorithm") - [Fused multiply–add](https://en.wikipedia.org/wiki/Fused_multiply%E2%80%93add "Fused multiply–add") - [Dadda multiplier](https://en.wikipedia.org/wiki/Dadda_multiplier "Dadda multiplier") - [Wallace tree](https://en.wikipedia.org/wiki/Wallace_tree "Wallace tree") - [BKM algorithm](https://en.wikipedia.org/wiki/BKM_algorithm "BKM algorithm") for complex logarithms and exponentials - [Kochanski multiplication](https://en.wikipedia.org/wiki/Kochanski_multiplication "Kochanski multiplication") for [modular](https://en.wikipedia.org/wiki/Modular_arithmetic "Modular arithmetic") multiplication - [Logical shift left](https://en.wikipedia.org/wiki/Logical_shift_left "Logical shift left") 1. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-1) Rather, Elizabeth D.; Colburn, Donald R.; Moore, Charles H. (1996) \[1993\]. ["The evolution of Forth"](http://www.forth.com/resources/evolution/index.html). In Bergin, Thomas J.; Gibson, Richard G. (eds.). History of programming languages---II. Association for Computing Machinery. pp. 625–670\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1145/234286.1057832](https://doi.org/10.1145%2F234286.1057832). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [0201895021](https://en.wikipedia.org/wiki/Special:BookSources/0201895021 "Special:BookSources/0201895021") . 2. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-2) Davies, A.C.; Fung, Y.T. (1977). ["Interfacing a hardware multiplier to a general-purpose microprocessor"](https://dx.doi.org/10.1016/0308-5953%2877%2990004-6). Microprocessors. 1 (7): 425–432\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1016/0308-5953(77)90004-6](https://doi.org/10.1016%2F0308-5953%2877%2990004-6). 3. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-3) [Rafiquzzaman, M.](https://en.wikipedia.org/wiki/Mohamed_Rafiquzzaman "Mohamed Rafiquzzaman") (2005). ["§2.5.1 Binary Arithmetic: Multiplication of Unsigned Binary Numbers"](https://books.google.com/books?id=1QZEawDm9uAC&pg=PA46). Fundamentals of Digital Logic and Microcomputer Design. [Wiley](https://en.wikipedia.org/wiki/John_Wiley_%26_Sons "John Wiley & Sons"). p. 46. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-0-47173349-2](https://en.wikipedia.org/wiki/Special:BookSources/978-0-47173349-2 "Special:BookSources/978-0-47173349-2") . 4. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-4) [Rafiquzzaman 2005](https://en.wikipedia.org/wiki/Binary_multiplier#CITEREFRafiquzzaman2005), [§7.3.3 Addition, Subtraction, Multiplication and Division of Signed and Unsigned Numbers p. 251](https://books.google.com/books?id=1QZEawDm9uAC&pg=PA251) 5. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-5) Kant, Krishna (2007). ["§2.11.2 16-Bit Microprocessors"](https://books.google.com/books?id=P-n3kelycHQC&pg=PA57). Microprocessors and Microcontrollers: Architecture, Programming and System Design 8085, 8086, 8051, 8096. PHI Learning. p. 57. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [9788120331914](https://en.wikipedia.org/wiki/Special:BookSources/9788120331914 "Special:BookSources/9788120331914") . 6. ^ [*a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-1) [c](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-rouholamini_6-2) Rouholamini, Mahnoush; Kavehie, Omid; Mirbaha, Amir-Pasha; Jasbi, Somaye Jafarali; Navi, Keivan. ["A New Design for 7:2 Compressors"](http://www.dl.edi-info.ir/A%20New%20Design%20for%2072%20Compressors.pdf) (PDF). 7. ^ [a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-leong_7-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-leong_7-1) Leong, Yuhao; Lo, HaiHiung; Drieberg, Michael; Sayuti, Abu Bakar; Sebastian, Patrick. ["Performance Comparison Review of 8-3 compressor on FPGA"](https://www.researchgate.net/publication/322218557). 8. ^ [a](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-chang_8-0) [b](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-chang_8-1) Peng Chang. ["A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design"](https://scholar.uwindsor.ca/cgi/viewcontent.cgi?article=8801&context=etd). 2008. 9. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Baugh-Wooley_1973_9-0)* Baugh, Charles Richmond; Wooley, Bruce A. (December 1973). "A Two's Complement Parallel Array Multiplication Algorithm". [IEEE Transactions on Computers](https://en.wikipedia.org/wiki/IEEE_Transactions_on_Computers "IEEE Transactions on Computers"). C-22 (12): 1045–1047\. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1109/T-C.1973.223648](https://doi.org/10.1109%2FT-C.1973.223648). [S2CID](https://en.wikipedia.org/wiki/S2CID_\(identifier\) "S2CID (identifier)") [7473784](https://api.semanticscholar.org/CorpusID:7473784). 10. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Hatamian-Cash_1986_10-0) Hatamian, Mehdi; Cash, Glenn (1986). ["A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS"](https://www.researchgate.net/publication/2981745). [IEEE Journal of Solid-State Circuits](https://en.wikipedia.org/wiki/IEEE_Journal_of_Solid-State_Circuits "IEEE Journal of Solid-State Circuits"). 21 (4): 505–513\. [Bibcode](https://en.wikipedia.org/wiki/Bibcode_\(identifier\) "Bibcode (identifier)"):[1986IJSSC..21..505H](https://ui.adsabs.harvard.edu/abs/1986IJSSC..21..505H). [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1109/jssc.1986.1052564](https://doi.org/10.1109%2Fjssc.1986.1052564). 11. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-Gebali_2003_11-0) Gebali, Fayez (2003). ["Baugh–Wooley Multiplier"](http://www.ece.uvic.ca/~fayez/courses/ceng465/lab_465/project2/multiplier.pdf) (PDF). [University of Victoria](https://en.wikipedia.org/wiki/University_of_Victoria "University of Victoria"), CENG 465 Lab 2. [Archived](https://web.archive.org/web/20180414230734/http://www.ece.uvic.ca/~fayez/courses/ceng465/lab_465/project2/multiplier.pdf) (PDF) from the original on 2018-04-14. Retrieved 2018-04-14. 12. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-ULVD_2015_12-0) Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer. [doi](https://en.wikipedia.org/wiki/Doi_\(identifier\) "Doi (identifier)"):[10\.1007/978-3-319-16136-5](https://doi.org/10.1007%2F978-3-319-16136-5). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-3-319-16135-8](https://en.wikipedia.org/wiki/Special:BookSources/978-3-319-16135-8 "Special:BookSources/978-3-319-16135-8") . [ISSN](https://en.wikipedia.org/wiki/ISSN_\(identifier\) "ISSN (identifier)") [1872-082X](https://search.worldcat.org/issn/1872-082X). [LCCN](https://en.wikipedia.org/wiki/LCCN_\(identifier\) "LCCN (identifier)") [2015935431](https://lccn.loc.gov/2015935431). 13. [^](https://en.wikipedia.org/wiki/Binary_multiplier#cite_ref-13) Parhami, Behrooz (2000). Computer Arithmetic: Algorithms and Hardware Designs. [Oxford University Press](https://en.wikipedia.org/wiki/Oxford_University_Press "Oxford University Press"). [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [0-19-512583-5](https://en.wikipedia.org/wiki/Special:BookSources/0-19-512583-5 "Special:BookSources/0-19-512583-5") . - Hennessy, John L.; Patterson, David A. (1990). "Section A.2, section A.9". Computer Architecture: A quantitative Approach. Morgan Kaufmann. pp. A–3..A–6, A–39..A–49. [ISBN](https://en.wikipedia.org/wiki/ISBN_\(identifier\) "ISBN (identifier)") [978-0-12383872-8](https://en.wikipedia.org/wiki/Special:BookSources/978-0-12383872-8 "Special:BookSources/978-0-12383872-8") . - [Multiplier Designs](http://www.andraka.com/multipli.php) targeted at [FPGAs](https://en.wikipedia.org/wiki/FPGA "FPGA") - [Binary Multiplier circuit using Half -Adders and digital gates.](http://www.fullchipdesign.com/binary_multiplier_digital.htm)
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